1626 lines
41 KiB
C
1626 lines
41 KiB
C
/*
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* sgtl5000.c -- SGTL5000 ALSA SoC Audio driver
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*
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* Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/pm.h>
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#include <linux/i2c.h>
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#include <linux/clk.h>
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#include <linux/regmap.h>
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#include <linux/regulator/driver.h>
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#include <linux/regulator/machine.h>
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#include <linux/regulator/consumer.h>
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#include <linux/of_device.h>
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#include <sound/core.h>
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#include <sound/tlv.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <sound/soc-dapm.h>
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#include <sound/initval.h>
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#include "sgtl5000.h"
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#define SGTL5000_DAP_REG_OFFSET 0x0100
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#define SGTL5000_MAX_REG_OFFSET 0x013A
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/* default value of sgtl5000 registers */
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static const struct reg_default sgtl5000_reg_defaults[] = {
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{ SGTL5000_CHIP_CLK_CTRL, 0x0008 },
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{ SGTL5000_CHIP_I2S_CTRL, 0x0010 },
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{ SGTL5000_CHIP_SSS_CTRL, 0x0010 },
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{ SGTL5000_CHIP_DAC_VOL, 0x3c3c },
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{ SGTL5000_CHIP_PAD_STRENGTH, 0x015f },
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{ SGTL5000_CHIP_ANA_HP_CTRL, 0x1818 },
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{ SGTL5000_CHIP_ANA_CTRL, 0x0111 },
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{ SGTL5000_CHIP_LINE_OUT_VOL, 0x0404 },
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{ SGTL5000_CHIP_ANA_POWER, 0x7060 },
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{ SGTL5000_CHIP_PLL_CTRL, 0x5000 },
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{ SGTL5000_DAP_BASS_ENHANCE, 0x0040 },
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{ SGTL5000_DAP_BASS_ENHANCE_CTRL, 0x051f },
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{ SGTL5000_DAP_SURROUND, 0x0040 },
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{ SGTL5000_DAP_EQ_BASS_BAND0, 0x002f },
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{ SGTL5000_DAP_EQ_BASS_BAND1, 0x002f },
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{ SGTL5000_DAP_EQ_BASS_BAND2, 0x002f },
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{ SGTL5000_DAP_EQ_BASS_BAND3, 0x002f },
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{ SGTL5000_DAP_EQ_BASS_BAND4, 0x002f },
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{ SGTL5000_DAP_MAIN_CHAN, 0x8000 },
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{ SGTL5000_DAP_AVC_CTRL, 0x0510 },
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{ SGTL5000_DAP_AVC_THRESHOLD, 0x1473 },
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{ SGTL5000_DAP_AVC_ATTACK, 0x0028 },
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{ SGTL5000_DAP_AVC_DECAY, 0x0050 },
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};
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/* regulator supplies for sgtl5000, VDDD is an optional external supply */
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enum sgtl5000_regulator_supplies {
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VDDA,
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VDDIO,
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VDDD,
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SGTL5000_SUPPLY_NUM
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};
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/* vddd is optional supply */
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static const char *supply_names[SGTL5000_SUPPLY_NUM] = {
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"VDDA",
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"VDDIO",
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"VDDD"
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};
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#define LDO_CONSUMER_NAME "VDDD_LDO"
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#define LDO_VOLTAGE 1200000
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static struct regulator_consumer_supply ldo_consumer[] = {
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REGULATOR_SUPPLY(LDO_CONSUMER_NAME, NULL),
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};
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static struct regulator_init_data ldo_init_data = {
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.constraints = {
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.min_uV = 1200000,
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.max_uV = 1200000,
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.valid_modes_mask = REGULATOR_MODE_NORMAL,
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.valid_ops_mask = REGULATOR_CHANGE_STATUS,
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},
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.num_consumer_supplies = 1,
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.consumer_supplies = &ldo_consumer[0],
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};
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/*
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* sgtl5000 internal ldo regulator,
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* enabled when VDDD not provided
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*/
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struct ldo_regulator {
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struct regulator_desc desc;
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struct regulator_dev *dev;
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int voltage;
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void *codec_data;
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bool enabled;
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};
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/* sgtl5000 private structure in codec */
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struct sgtl5000_priv {
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int sysclk; /* sysclk rate */
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int master; /* i2s master or not */
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int fmt; /* i2s data format */
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struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM];
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struct ldo_regulator *ldo;
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struct regmap *regmap;
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struct clk *mclk;
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};
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/*
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* mic_bias power on/off share the same register bits with
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* output impedance of mic bias, when power on mic bias, we
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* need reclaim it to impedance value.
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* 0x0 = Powered off
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* 0x1 = 2Kohm
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* 0x2 = 4Kohm
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* 0x3 = 8Kohm
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*/
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static int mic_bias_event(struct snd_soc_dapm_widget *w,
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struct snd_kcontrol *kcontrol, int event)
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{
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switch (event) {
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case SND_SOC_DAPM_POST_PMU:
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/* change mic bias resistor to 4Kohm */
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snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
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SGTL5000_BIAS_R_MASK,
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SGTL5000_BIAS_R_4k << SGTL5000_BIAS_R_SHIFT);
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break;
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case SND_SOC_DAPM_PRE_PMD:
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snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
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SGTL5000_BIAS_R_MASK, 0);
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break;
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}
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return 0;
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}
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/*
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* As manual described, ADC/DAC only works when VAG powerup,
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* So enabled VAG before ADC/DAC up.
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* In power down case, we need wait 400ms when vag fully ramped down.
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*/
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static int power_vag_event(struct snd_soc_dapm_widget *w,
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struct snd_kcontrol *kcontrol, int event)
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{
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const u32 mask = SGTL5000_DAC_POWERUP | SGTL5000_ADC_POWERUP;
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switch (event) {
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case SND_SOC_DAPM_POST_PMU:
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snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
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SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
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break;
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case SND_SOC_DAPM_PRE_PMD:
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/*
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* Don't clear VAG_POWERUP, when both DAC and ADC are
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* operational to prevent inadvertently starving the
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* other one of them.
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*/
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if ((snd_soc_read(w->codec, SGTL5000_CHIP_ANA_POWER) &
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mask) != mask) {
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snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
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SGTL5000_VAG_POWERUP, 0);
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msleep(400);
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}
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break;
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default:
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break;
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}
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return 0;
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}
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/* input sources for ADC */
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static const char *adc_mux_text[] = {
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"MIC_IN", "LINE_IN"
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};
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static const struct soc_enum adc_enum =
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SOC_ENUM_SINGLE(SGTL5000_CHIP_ANA_CTRL, 2, 2, adc_mux_text);
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static const struct snd_kcontrol_new adc_mux =
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SOC_DAPM_ENUM("Capture Mux", adc_enum);
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/* input sources for DAC */
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static const char *dac_mux_text[] = {
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"DAC", "LINE_IN"
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};
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static const struct soc_enum dac_enum =
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SOC_ENUM_SINGLE(SGTL5000_CHIP_ANA_CTRL, 6, 2, dac_mux_text);
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static const struct snd_kcontrol_new dac_mux =
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SOC_DAPM_ENUM("Headphone Mux", dac_enum);
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static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
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SND_SOC_DAPM_INPUT("LINE_IN"),
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SND_SOC_DAPM_INPUT("MIC_IN"),
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SND_SOC_DAPM_OUTPUT("HP_OUT"),
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SND_SOC_DAPM_OUTPUT("LINE_OUT"),
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SND_SOC_DAPM_SUPPLY("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0,
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mic_bias_event,
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SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
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SND_SOC_DAPM_PGA("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0),
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SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0),
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SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux),
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SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &dac_mux),
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/* aif for i2s input */
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SND_SOC_DAPM_AIF_IN("AIFIN", "Playback",
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0, SGTL5000_CHIP_DIG_POWER,
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0, 0),
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/* aif for i2s output */
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SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture",
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0, SGTL5000_CHIP_DIG_POWER,
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1, 0),
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SND_SOC_DAPM_ADC("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0),
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SND_SOC_DAPM_DAC("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0),
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SND_SOC_DAPM_PRE("VAG_POWER_PRE", power_vag_event),
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SND_SOC_DAPM_POST("VAG_POWER_POST", power_vag_event),
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};
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/* routes for sgtl5000 */
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static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = {
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{"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */
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{"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */
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{"ADC", NULL, "Capture Mux"}, /* adc_mux --> adc */
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{"AIFOUT", NULL, "ADC"}, /* adc --> i2s_out */
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{"DAC", NULL, "AIFIN"}, /* i2s-->dac,skip audio mux */
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{"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */
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{"LO", NULL, "DAC"}, /* dac --> line_out */
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{"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */
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{"HP", NULL, "Headphone Mux"}, /* hp_mux --> hp */
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{"LINE_OUT", NULL, "LO"},
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{"HP_OUT", NULL, "HP"},
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};
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/* custom function to fetch info of PCM playback volume */
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static int dac_info_volsw(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_info *uinfo)
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{
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uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
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uinfo->count = 2;
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uinfo->value.integer.min = 0;
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uinfo->value.integer.max = 0xfc - 0x3c;
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return 0;
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}
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/*
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* custom function to get of PCM playback volume
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*
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* dac volume register
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* 15-------------8-7--------------0
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* | R channel vol | L channel vol |
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* -------------------------------
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*
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* PCM volume with 0.5017 dB steps from 0 to -90 dB
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*
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* register values map to dB
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* 0x3B and less = Reserved
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* 0x3C = 0 dB
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* 0x3D = -0.5 dB
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* 0xF0 = -90 dB
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* 0xFC and greater = Muted
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*
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* register value map to userspace value
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*
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* register value 0x3c(0dB) 0xf0(-90dB)0xfc
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* ------------------------------
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* userspace value 0xc0 0
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*/
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static int dac_get_volsw(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
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int reg;
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int l;
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int r;
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reg = snd_soc_read(codec, SGTL5000_CHIP_DAC_VOL);
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/* get left channel volume */
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l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT;
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/* get right channel volume */
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r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT;
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/* make sure value fall in (0x3c,0xfc) */
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l = clamp(l, 0x3c, 0xfc);
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r = clamp(r, 0x3c, 0xfc);
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/* invert it and map to userspace value */
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l = 0xfc - l;
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r = 0xfc - r;
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ucontrol->value.integer.value[0] = l;
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ucontrol->value.integer.value[1] = r;
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return 0;
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}
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/*
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* custom function to put of PCM playback volume
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*
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* dac volume register
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* 15-------------8-7--------------0
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* | R channel vol | L channel vol |
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* -------------------------------
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*
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* PCM volume with 0.5017 dB steps from 0 to -90 dB
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*
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* register values map to dB
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* 0x3B and less = Reserved
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* 0x3C = 0 dB
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* 0x3D = -0.5 dB
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* 0xF0 = -90 dB
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* 0xFC and greater = Muted
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*
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* userspace value map to register value
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*
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* userspace value 0xc0 0
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* ------------------------------
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* register value 0x3c(0dB) 0xf0(-90dB)0xfc
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*/
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static int dac_put_volsw(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
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int reg;
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int l;
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int r;
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l = ucontrol->value.integer.value[0];
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r = ucontrol->value.integer.value[1];
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/* make sure userspace volume fall in (0, 0xfc-0x3c) */
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l = clamp(l, 0, 0xfc - 0x3c);
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r = clamp(r, 0, 0xfc - 0x3c);
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/* invert it, get the value can be set to register */
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l = 0xfc - l;
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r = 0xfc - r;
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/* shift to get the register value */
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reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT |
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r << SGTL5000_DAC_VOL_RIGHT_SHIFT;
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snd_soc_write(codec, SGTL5000_CHIP_DAC_VOL, reg);
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return 0;
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}
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static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0);
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/* tlv for mic gain, 0db 20db 30db 40db */
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static const unsigned int mic_gain_tlv[] = {
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TLV_DB_RANGE_HEAD(2),
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0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
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1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0),
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};
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/* tlv for hp volume, -51.5db to 12.0db, step .5db */
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static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0);
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static const struct snd_kcontrol_new sgtl5000_snd_controls[] = {
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/* SOC_DOUBLE_S8_TLV with invert */
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{
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.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
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.name = "PCM Playback Volume",
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.access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |
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SNDRV_CTL_ELEM_ACCESS_READWRITE,
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.info = dac_info_volsw,
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.get = dac_get_volsw,
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.put = dac_put_volsw,
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},
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SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0),
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SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)",
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SGTL5000_CHIP_ANA_ADC_CTRL,
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8, 1, 0, capture_6db_attenuate),
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SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0),
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SOC_DOUBLE_TLV("Headphone Playback Volume",
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SGTL5000_CHIP_ANA_HP_CTRL,
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0, 8,
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0x7f, 1,
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headphone_volume),
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SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL,
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5, 1, 0),
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SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL,
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0, 3, 0, mic_gain_tlv),
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};
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/* mute the codec used by alsa core */
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static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute)
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{
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struct snd_soc_codec *codec = codec_dai->codec;
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u16 adcdac_ctrl = SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT;
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snd_soc_update_bits(codec, SGTL5000_CHIP_ADCDAC_CTRL,
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adcdac_ctrl, mute ? adcdac_ctrl : 0);
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return 0;
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}
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/* set codec format */
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static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
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{
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struct snd_soc_codec *codec = codec_dai->codec;
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struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
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u16 i2sctl = 0;
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sgtl5000->master = 0;
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/*
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* i2s clock and frame master setting.
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* ONLY support:
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* - clock and frame slave,
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* - clock and frame master
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*/
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBS_CFS:
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break;
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case SND_SOC_DAIFMT_CBM_CFM:
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i2sctl |= SGTL5000_I2S_MASTER;
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sgtl5000->master = 1;
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break;
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default:
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return -EINVAL;
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}
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/* setting i2s data format */
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_DSP_A:
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i2sctl |= SGTL5000_I2S_MODE_PCM;
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break;
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case SND_SOC_DAIFMT_DSP_B:
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i2sctl |= SGTL5000_I2S_MODE_PCM;
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|
i2sctl |= SGTL5000_I2S_LRALIGN;
|
|
break;
|
|
case SND_SOC_DAIFMT_I2S:
|
|
i2sctl |= SGTL5000_I2S_MODE_I2S_LJ;
|
|
break;
|
|
case SND_SOC_DAIFMT_RIGHT_J:
|
|
i2sctl |= SGTL5000_I2S_MODE_RJ;
|
|
i2sctl |= SGTL5000_I2S_LRPOL;
|
|
break;
|
|
case SND_SOC_DAIFMT_LEFT_J:
|
|
i2sctl |= SGTL5000_I2S_MODE_I2S_LJ;
|
|
i2sctl |= SGTL5000_I2S_LRALIGN;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
|
|
|
|
/* Clock inversion */
|
|
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
|
|
case SND_SOC_DAIFMT_NB_NF:
|
|
break;
|
|
case SND_SOC_DAIFMT_IB_NF:
|
|
i2sctl |= SGTL5000_I2S_SCLK_INV;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
snd_soc_write(codec, SGTL5000_CHIP_I2S_CTRL, i2sctl);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* set codec sysclk */
|
|
static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai,
|
|
int clk_id, unsigned int freq, int dir)
|
|
{
|
|
struct snd_soc_codec *codec = codec_dai->codec;
|
|
struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
|
|
|
|
switch (clk_id) {
|
|
case SGTL5000_SYSCLK:
|
|
sgtl5000->sysclk = freq;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* set clock according to i2s frame clock,
|
|
* sgtl5000 provide 2 clock sources.
|
|
* 1. sys_mclk. sample freq can only configure to
|
|
* 1/256, 1/384, 1/512 of sys_mclk.
|
|
* 2. pll. can derive any audio clocks.
|
|
*
|
|
* clock setting rules:
|
|
* 1. in slave mode, only sys_mclk can use.
|
|
* 2. as constraint by sys_mclk, sample freq should
|
|
* set to 32k, 44.1k and above.
|
|
* 3. using sys_mclk prefer to pll to save power.
|
|
*/
|
|
static int sgtl5000_set_clock(struct snd_soc_codec *codec, int frame_rate)
|
|
{
|
|
struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
|
|
int clk_ctl = 0;
|
|
int sys_fs; /* sample freq */
|
|
|
|
/*
|
|
* sample freq should be divided by frame clock,
|
|
* if frame clock lower than 44.1khz, sample feq should set to
|
|
* 32khz or 44.1khz.
|
|
*/
|
|
switch (frame_rate) {
|
|
case 8000:
|
|
case 16000:
|
|
sys_fs = 32000;
|
|
break;
|
|
case 11025:
|
|
case 22050:
|
|
sys_fs = 44100;
|
|
break;
|
|
default:
|
|
sys_fs = frame_rate;
|
|
break;
|
|
}
|
|
|
|
/* set divided factor of frame clock */
|
|
switch (sys_fs / frame_rate) {
|
|
case 4:
|
|
clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT;
|
|
break;
|
|
case 2:
|
|
clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT;
|
|
break;
|
|
case 1:
|
|
clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* set the sys_fs according to frame rate */
|
|
switch (sys_fs) {
|
|
case 32000:
|
|
clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT;
|
|
break;
|
|
case 44100:
|
|
clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT;
|
|
break;
|
|
case 48000:
|
|
clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT;
|
|
break;
|
|
case 96000:
|
|
clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT;
|
|
break;
|
|
default:
|
|
dev_err(codec->dev, "frame rate %d not supported\n",
|
|
frame_rate);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/*
|
|
* calculate the divider of mclk/sample_freq,
|
|
* factor of freq =96k can only be 256, since mclk in range (12m,27m)
|
|
*/
|
|
switch (sgtl5000->sysclk / sys_fs) {
|
|
case 256:
|
|
clk_ctl |= SGTL5000_MCLK_FREQ_256FS <<
|
|
SGTL5000_MCLK_FREQ_SHIFT;
|
|
break;
|
|
case 384:
|
|
clk_ctl |= SGTL5000_MCLK_FREQ_384FS <<
|
|
SGTL5000_MCLK_FREQ_SHIFT;
|
|
break;
|
|
case 512:
|
|
clk_ctl |= SGTL5000_MCLK_FREQ_512FS <<
|
|
SGTL5000_MCLK_FREQ_SHIFT;
|
|
break;
|
|
default:
|
|
/* if mclk not satisify the divider, use pll */
|
|
if (sgtl5000->master) {
|
|
clk_ctl |= SGTL5000_MCLK_FREQ_PLL <<
|
|
SGTL5000_MCLK_FREQ_SHIFT;
|
|
} else {
|
|
dev_err(codec->dev,
|
|
"PLL not supported in slave mode\n");
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
/* if using pll, please check manual 6.4.2 for detail */
|
|
if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) {
|
|
u64 out, t;
|
|
int div2;
|
|
int pll_ctl;
|
|
unsigned int in, int_div, frac_div;
|
|
|
|
if (sgtl5000->sysclk > 17000000) {
|
|
div2 = 1;
|
|
in = sgtl5000->sysclk / 2;
|
|
} else {
|
|
div2 = 0;
|
|
in = sgtl5000->sysclk;
|
|
}
|
|
if (sys_fs == 44100)
|
|
out = 180633600;
|
|
else
|
|
out = 196608000;
|
|
t = do_div(out, in);
|
|
int_div = out;
|
|
t *= 2048;
|
|
do_div(t, in);
|
|
frac_div = t;
|
|
pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT |
|
|
frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT;
|
|
|
|
snd_soc_write(codec, SGTL5000_CHIP_PLL_CTRL, pll_ctl);
|
|
if (div2)
|
|
snd_soc_update_bits(codec,
|
|
SGTL5000_CHIP_CLK_TOP_CTRL,
|
|
SGTL5000_INPUT_FREQ_DIV2,
|
|
SGTL5000_INPUT_FREQ_DIV2);
|
|
else
|
|
snd_soc_update_bits(codec,
|
|
SGTL5000_CHIP_CLK_TOP_CTRL,
|
|
SGTL5000_INPUT_FREQ_DIV2,
|
|
0);
|
|
|
|
/* power up pll */
|
|
snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
|
|
SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
|
|
SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP);
|
|
|
|
/* if using pll, clk_ctrl must be set after pll power up */
|
|
snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
|
|
} else {
|
|
/* otherwise, clk_ctrl must be set before pll power down */
|
|
snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
|
|
|
|
/* power down pll */
|
|
snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
|
|
SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
|
|
0);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Set PCM DAI bit size and sample rate.
|
|
* input: params_rate, params_fmt
|
|
*/
|
|
static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream,
|
|
struct snd_pcm_hw_params *params,
|
|
struct snd_soc_dai *dai)
|
|
{
|
|
struct snd_soc_codec *codec = dai->codec;
|
|
struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
|
|
int channels = params_channels(params);
|
|
int i2s_ctl = 0;
|
|
int stereo;
|
|
int ret;
|
|
|
|
/* sysclk should already set */
|
|
if (!sgtl5000->sysclk) {
|
|
dev_err(codec->dev, "%s: set sysclk first!\n", __func__);
|
|
return -EFAULT;
|
|
}
|
|
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
|
|
stereo = SGTL5000_DAC_STEREO;
|
|
else
|
|
stereo = SGTL5000_ADC_STEREO;
|
|
|
|
/* set mono to save power */
|
|
snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, stereo,
|
|
channels == 1 ? 0 : stereo);
|
|
|
|
/* set codec clock base on lrclk */
|
|
ret = sgtl5000_set_clock(codec, params_rate(params));
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* set i2s data format */
|
|
switch (params_format(params)) {
|
|
case SNDRV_PCM_FORMAT_S16_LE:
|
|
if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
|
|
return -EINVAL;
|
|
i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT;
|
|
i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS <<
|
|
SGTL5000_I2S_SCLKFREQ_SHIFT;
|
|
break;
|
|
case SNDRV_PCM_FORMAT_S20_3LE:
|
|
i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT;
|
|
i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
|
|
SGTL5000_I2S_SCLKFREQ_SHIFT;
|
|
break;
|
|
case SNDRV_PCM_FORMAT_S24_LE:
|
|
i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT;
|
|
i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
|
|
SGTL5000_I2S_SCLKFREQ_SHIFT;
|
|
break;
|
|
case SNDRV_PCM_FORMAT_S32_LE:
|
|
if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
|
|
return -EINVAL;
|
|
i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT;
|
|
i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
|
|
SGTL5000_I2S_SCLKFREQ_SHIFT;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
snd_soc_update_bits(codec, SGTL5000_CHIP_I2S_CTRL,
|
|
SGTL5000_I2S_DLEN_MASK | SGTL5000_I2S_SCLKFREQ_MASK,
|
|
i2s_ctl);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_REGULATOR
|
|
static int ldo_regulator_is_enabled(struct regulator_dev *dev)
|
|
{
|
|
struct ldo_regulator *ldo = rdev_get_drvdata(dev);
|
|
|
|
return ldo->enabled;
|
|
}
|
|
|
|
static int ldo_regulator_enable(struct regulator_dev *dev)
|
|
{
|
|
struct ldo_regulator *ldo = rdev_get_drvdata(dev);
|
|
struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data;
|
|
int reg;
|
|
|
|
if (ldo_regulator_is_enabled(dev))
|
|
return 0;
|
|
|
|
/* set regulator value firstly */
|
|
reg = (1600 - ldo->voltage / 1000) / 50;
|
|
reg = clamp(reg, 0x0, 0xf);
|
|
|
|
/* amend the voltage value, unit: uV */
|
|
ldo->voltage = (1600 - reg * 50) * 1000;
|
|
|
|
/* set voltage to register */
|
|
snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
|
|
SGTL5000_LINREG_VDDD_MASK, reg);
|
|
|
|
snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
|
|
SGTL5000_LINEREG_D_POWERUP,
|
|
SGTL5000_LINEREG_D_POWERUP);
|
|
|
|
/* when internal ldo enabled, simple digital power can be disabled */
|
|
snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
|
|
SGTL5000_LINREG_SIMPLE_POWERUP,
|
|
0);
|
|
|
|
ldo->enabled = 1;
|
|
return 0;
|
|
}
|
|
|
|
static int ldo_regulator_disable(struct regulator_dev *dev)
|
|
{
|
|
struct ldo_regulator *ldo = rdev_get_drvdata(dev);
|
|
struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data;
|
|
|
|
snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
|
|
SGTL5000_LINEREG_D_POWERUP,
|
|
0);
|
|
|
|
/* clear voltage info */
|
|
snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
|
|
SGTL5000_LINREG_VDDD_MASK, 0);
|
|
|
|
ldo->enabled = 0;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ldo_regulator_get_voltage(struct regulator_dev *dev)
|
|
{
|
|
struct ldo_regulator *ldo = rdev_get_drvdata(dev);
|
|
|
|
return ldo->voltage;
|
|
}
|
|
|
|
static struct regulator_ops ldo_regulator_ops = {
|
|
.is_enabled = ldo_regulator_is_enabled,
|
|
.enable = ldo_regulator_enable,
|
|
.disable = ldo_regulator_disable,
|
|
.get_voltage = ldo_regulator_get_voltage,
|
|
};
|
|
|
|
static int ldo_regulator_register(struct snd_soc_codec *codec,
|
|
struct regulator_init_data *init_data,
|
|
int voltage)
|
|
{
|
|
struct ldo_regulator *ldo;
|
|
struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
|
|
struct regulator_config config = { };
|
|
|
|
ldo = kzalloc(sizeof(struct ldo_regulator), GFP_KERNEL);
|
|
|
|
if (!ldo) {
|
|
dev_err(codec->dev, "failed to allocate ldo_regulator\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
ldo->desc.name = kstrdup(dev_name(codec->dev), GFP_KERNEL);
|
|
if (!ldo->desc.name) {
|
|
kfree(ldo);
|
|
dev_err(codec->dev, "failed to allocate decs name memory\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
ldo->desc.type = REGULATOR_VOLTAGE;
|
|
ldo->desc.owner = THIS_MODULE;
|
|
ldo->desc.ops = &ldo_regulator_ops;
|
|
ldo->desc.n_voltages = 1;
|
|
|
|
ldo->codec_data = codec;
|
|
ldo->voltage = voltage;
|
|
|
|
config.dev = codec->dev;
|
|
config.driver_data = ldo;
|
|
config.init_data = init_data;
|
|
|
|
ldo->dev = regulator_register(&ldo->desc, &config);
|
|
if (IS_ERR(ldo->dev)) {
|
|
int ret = PTR_ERR(ldo->dev);
|
|
|
|
dev_err(codec->dev, "failed to register regulator\n");
|
|
kfree(ldo->desc.name);
|
|
kfree(ldo);
|
|
|
|
return ret;
|
|
}
|
|
sgtl5000->ldo = ldo;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ldo_regulator_remove(struct snd_soc_codec *codec)
|
|
{
|
|
struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
|
|
struct ldo_regulator *ldo = sgtl5000->ldo;
|
|
|
|
if (!ldo)
|
|
return 0;
|
|
|
|
regulator_unregister(ldo->dev);
|
|
kfree(ldo->desc.name);
|
|
kfree(ldo);
|
|
|
|
return 0;
|
|
}
|
|
#else
|
|
static int ldo_regulator_register(struct snd_soc_codec *codec,
|
|
struct regulator_init_data *init_data,
|
|
int voltage)
|
|
{
|
|
dev_err(codec->dev, "this setup needs regulator support in the kernel\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
static int ldo_regulator_remove(struct snd_soc_codec *codec)
|
|
{
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* set dac bias
|
|
* common state changes:
|
|
* startup:
|
|
* off --> standby --> prepare --> on
|
|
* standby --> prepare --> on
|
|
*
|
|
* stop:
|
|
* on --> prepare --> standby
|
|
*/
|
|
static int sgtl5000_set_bias_level(struct snd_soc_codec *codec,
|
|
enum snd_soc_bias_level level)
|
|
{
|
|
int ret;
|
|
struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
|
|
|
|
switch (level) {
|
|
case SND_SOC_BIAS_ON:
|
|
case SND_SOC_BIAS_PREPARE:
|
|
break;
|
|
case SND_SOC_BIAS_STANDBY:
|
|
if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
|
|
ret = regulator_bulk_enable(
|
|
ARRAY_SIZE(sgtl5000->supplies),
|
|
sgtl5000->supplies);
|
|
if (ret)
|
|
return ret;
|
|
udelay(10);
|
|
|
|
regcache_cache_only(sgtl5000->regmap, false);
|
|
|
|
ret = regcache_sync(sgtl5000->regmap);
|
|
if (ret != 0) {
|
|
dev_err(codec->dev,
|
|
"Failed to restore cache: %d\n", ret);
|
|
|
|
regcache_cache_only(sgtl5000->regmap, true);
|
|
regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
|
|
sgtl5000->supplies);
|
|
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
break;
|
|
case SND_SOC_BIAS_OFF:
|
|
regcache_cache_only(sgtl5000->regmap, true);
|
|
regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
|
|
sgtl5000->supplies);
|
|
break;
|
|
}
|
|
|
|
codec->dapm.bias_level = level;
|
|
return 0;
|
|
}
|
|
|
|
#define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
|
|
SNDRV_PCM_FMTBIT_S20_3LE |\
|
|
SNDRV_PCM_FMTBIT_S24_LE |\
|
|
SNDRV_PCM_FMTBIT_S32_LE)
|
|
|
|
static const struct snd_soc_dai_ops sgtl5000_ops = {
|
|
.hw_params = sgtl5000_pcm_hw_params,
|
|
.digital_mute = sgtl5000_digital_mute,
|
|
.set_fmt = sgtl5000_set_dai_fmt,
|
|
.set_sysclk = sgtl5000_set_dai_sysclk,
|
|
};
|
|
|
|
static struct snd_soc_dai_driver sgtl5000_dai = {
|
|
.name = "sgtl5000",
|
|
.playback = {
|
|
.stream_name = "Playback",
|
|
.channels_min = 1,
|
|
.channels_max = 2,
|
|
/*
|
|
* only support 8~48K + 96K,
|
|
* TODO modify hw_param to support more
|
|
*/
|
|
.rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
|
|
.formats = SGTL5000_FORMATS,
|
|
},
|
|
.capture = {
|
|
.stream_name = "Capture",
|
|
.channels_min = 1,
|
|
.channels_max = 2,
|
|
.rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
|
|
.formats = SGTL5000_FORMATS,
|
|
},
|
|
.ops = &sgtl5000_ops,
|
|
.symmetric_rates = 1,
|
|
};
|
|
|
|
static bool sgtl5000_volatile(struct device *dev, unsigned int reg)
|
|
{
|
|
switch (reg) {
|
|
case SGTL5000_CHIP_ID:
|
|
case SGTL5000_CHIP_ADCDAC_CTRL:
|
|
case SGTL5000_CHIP_ANA_STATUS:
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
static bool sgtl5000_readable(struct device *dev, unsigned int reg)
|
|
{
|
|
switch (reg) {
|
|
case SGTL5000_CHIP_ID:
|
|
case SGTL5000_CHIP_DIG_POWER:
|
|
case SGTL5000_CHIP_CLK_CTRL:
|
|
case SGTL5000_CHIP_I2S_CTRL:
|
|
case SGTL5000_CHIP_SSS_CTRL:
|
|
case SGTL5000_CHIP_ADCDAC_CTRL:
|
|
case SGTL5000_CHIP_DAC_VOL:
|
|
case SGTL5000_CHIP_PAD_STRENGTH:
|
|
case SGTL5000_CHIP_ANA_ADC_CTRL:
|
|
case SGTL5000_CHIP_ANA_HP_CTRL:
|
|
case SGTL5000_CHIP_ANA_CTRL:
|
|
case SGTL5000_CHIP_LINREG_CTRL:
|
|
case SGTL5000_CHIP_REF_CTRL:
|
|
case SGTL5000_CHIP_MIC_CTRL:
|
|
case SGTL5000_CHIP_LINE_OUT_CTRL:
|
|
case SGTL5000_CHIP_LINE_OUT_VOL:
|
|
case SGTL5000_CHIP_ANA_POWER:
|
|
case SGTL5000_CHIP_PLL_CTRL:
|
|
case SGTL5000_CHIP_CLK_TOP_CTRL:
|
|
case SGTL5000_CHIP_ANA_STATUS:
|
|
case SGTL5000_CHIP_SHORT_CTRL:
|
|
case SGTL5000_CHIP_ANA_TEST2:
|
|
case SGTL5000_DAP_CTRL:
|
|
case SGTL5000_DAP_PEQ:
|
|
case SGTL5000_DAP_BASS_ENHANCE:
|
|
case SGTL5000_DAP_BASS_ENHANCE_CTRL:
|
|
case SGTL5000_DAP_AUDIO_EQ:
|
|
case SGTL5000_DAP_SURROUND:
|
|
case SGTL5000_DAP_FLT_COEF_ACCESS:
|
|
case SGTL5000_DAP_COEF_WR_B0_MSB:
|
|
case SGTL5000_DAP_COEF_WR_B0_LSB:
|
|
case SGTL5000_DAP_EQ_BASS_BAND0:
|
|
case SGTL5000_DAP_EQ_BASS_BAND1:
|
|
case SGTL5000_DAP_EQ_BASS_BAND2:
|
|
case SGTL5000_DAP_EQ_BASS_BAND3:
|
|
case SGTL5000_DAP_EQ_BASS_BAND4:
|
|
case SGTL5000_DAP_MAIN_CHAN:
|
|
case SGTL5000_DAP_MIX_CHAN:
|
|
case SGTL5000_DAP_AVC_CTRL:
|
|
case SGTL5000_DAP_AVC_THRESHOLD:
|
|
case SGTL5000_DAP_AVC_ATTACK:
|
|
case SGTL5000_DAP_AVC_DECAY:
|
|
case SGTL5000_DAP_COEF_WR_B1_MSB:
|
|
case SGTL5000_DAP_COEF_WR_B1_LSB:
|
|
case SGTL5000_DAP_COEF_WR_B2_MSB:
|
|
case SGTL5000_DAP_COEF_WR_B2_LSB:
|
|
case SGTL5000_DAP_COEF_WR_A1_MSB:
|
|
case SGTL5000_DAP_COEF_WR_A1_LSB:
|
|
case SGTL5000_DAP_COEF_WR_A2_MSB:
|
|
case SGTL5000_DAP_COEF_WR_A2_LSB:
|
|
return true;
|
|
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_SUSPEND
|
|
static int sgtl5000_suspend(struct snd_soc_codec *codec)
|
|
{
|
|
sgtl5000_set_bias_level(codec, SND_SOC_BIAS_OFF);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* restore all sgtl5000 registers,
|
|
* since a big hole between dap and regular registers,
|
|
* we will restore them respectively.
|
|
*/
|
|
static int sgtl5000_restore_regs(struct snd_soc_codec *codec)
|
|
{
|
|
u16 *cache = codec->reg_cache;
|
|
u16 reg;
|
|
|
|
/* restore regular registers */
|
|
for (reg = 0; reg <= SGTL5000_CHIP_SHORT_CTRL; reg += 2) {
|
|
|
|
/* These regs should restore in particular order */
|
|
if (reg == SGTL5000_CHIP_ANA_POWER ||
|
|
reg == SGTL5000_CHIP_CLK_CTRL ||
|
|
reg == SGTL5000_CHIP_LINREG_CTRL ||
|
|
reg == SGTL5000_CHIP_LINE_OUT_CTRL ||
|
|
reg == SGTL5000_CHIP_REF_CTRL)
|
|
continue;
|
|
|
|
snd_soc_write(codec, reg, cache[reg]);
|
|
}
|
|
|
|
/* restore dap registers */
|
|
for (reg = SGTL5000_DAP_REG_OFFSET; reg < SGTL5000_MAX_REG_OFFSET; reg += 2)
|
|
snd_soc_write(codec, reg, cache[reg]);
|
|
|
|
/*
|
|
* restore these regs according to the power setting sequence in
|
|
* sgtl5000_set_power_regs() and clock setting sequence in
|
|
* sgtl5000_set_clock().
|
|
*
|
|
* The order of restore is:
|
|
* 1. SGTL5000_CHIP_CLK_CTRL MCLK_FREQ bits (1:0) should be restore after
|
|
* SGTL5000_CHIP_ANA_POWER PLL bits set
|
|
* 2. SGTL5000_CHIP_LINREG_CTRL should be set before
|
|
* SGTL5000_CHIP_ANA_POWER LINREG_D restored
|
|
* 3. SGTL5000_CHIP_REF_CTRL controls Analog Ground Voltage,
|
|
* prefer to resotre it after SGTL5000_CHIP_ANA_POWER restored
|
|
*/
|
|
snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL,
|
|
cache[SGTL5000_CHIP_LINREG_CTRL]);
|
|
|
|
snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER,
|
|
cache[SGTL5000_CHIP_ANA_POWER]);
|
|
|
|
snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL,
|
|
cache[SGTL5000_CHIP_CLK_CTRL]);
|
|
|
|
snd_soc_write(codec, SGTL5000_CHIP_REF_CTRL,
|
|
cache[SGTL5000_CHIP_REF_CTRL]);
|
|
|
|
snd_soc_write(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
|
|
cache[SGTL5000_CHIP_LINE_OUT_CTRL]);
|
|
return 0;
|
|
}
|
|
|
|
static int sgtl5000_resume(struct snd_soc_codec *codec)
|
|
{
|
|
/* Bring the codec back up to standby to enable regulators */
|
|
sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
|
|
|
|
/* Restore registers by cached in memory */
|
|
sgtl5000_restore_regs(codec);
|
|
return 0;
|
|
}
|
|
#else
|
|
#define sgtl5000_suspend NULL
|
|
#define sgtl5000_resume NULL
|
|
#endif /* CONFIG_SUSPEND */
|
|
|
|
/*
|
|
* sgtl5000 has 3 internal power supplies:
|
|
* 1. VAG, normally set to vdda/2
|
|
* 2. chargepump, set to different value
|
|
* according to voltage of vdda and vddio
|
|
* 3. line out VAG, normally set to vddio/2
|
|
*
|
|
* and should be set according to:
|
|
* 1. vddd provided by external or not
|
|
* 2. vdda and vddio voltage value. > 3.1v or not
|
|
* 3. chip revision >=0x11 or not. If >=0x11, not use external vddd.
|
|
*/
|
|
static int sgtl5000_set_power_regs(struct snd_soc_codec *codec)
|
|
{
|
|
int vddd;
|
|
int vdda;
|
|
int vddio;
|
|
u16 ana_pwr;
|
|
u16 lreg_ctrl;
|
|
int vag;
|
|
struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
|
|
|
|
vdda = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer);
|
|
vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer);
|
|
vddd = regulator_get_voltage(sgtl5000->supplies[VDDD].consumer);
|
|
|
|
vdda = vdda / 1000;
|
|
vddio = vddio / 1000;
|
|
vddd = vddd / 1000;
|
|
|
|
if (vdda <= 0 || vddio <= 0 || vddd < 0) {
|
|
dev_err(codec->dev, "regulator voltage not set correctly\n");
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* according to datasheet, maximum voltage of supplies */
|
|
if (vdda > 3600 || vddio > 3600 || vddd > 1980) {
|
|
dev_err(codec->dev,
|
|
"exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n",
|
|
vdda, vddio, vddd);
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* reset value */
|
|
ana_pwr = snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER);
|
|
ana_pwr |= SGTL5000_DAC_STEREO |
|
|
SGTL5000_ADC_STEREO |
|
|
SGTL5000_REFTOP_POWERUP;
|
|
lreg_ctrl = snd_soc_read(codec, SGTL5000_CHIP_LINREG_CTRL);
|
|
|
|
if (vddio < 3100 && vdda < 3100) {
|
|
/* enable internal oscillator used for charge pump */
|
|
snd_soc_update_bits(codec, SGTL5000_CHIP_CLK_TOP_CTRL,
|
|
SGTL5000_INT_OSC_EN,
|
|
SGTL5000_INT_OSC_EN);
|
|
/* Enable VDDC charge pump */
|
|
ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP;
|
|
} else if (vddio >= 3100 && vdda >= 3100) {
|
|
/*
|
|
* if vddio and vddd > 3.1v,
|
|
* charge pump should be clean before set ana_pwr
|
|
*/
|
|
snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
|
|
SGTL5000_VDDC_CHRGPMP_POWERUP, 0);
|
|
|
|
/* VDDC use VDDIO rail */
|
|
lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD;
|
|
lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO <<
|
|
SGTL5000_VDDC_MAN_ASSN_SHIFT;
|
|
}
|
|
|
|
snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl);
|
|
|
|
snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, ana_pwr);
|
|
|
|
/* set voltage to register */
|
|
snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
|
|
SGTL5000_LINREG_VDDD_MASK, 0x8);
|
|
|
|
/*
|
|
* if vddd linear reg has been enabled,
|
|
* simple digital supply should be clear to get
|
|
* proper VDDD voltage.
|
|
*/
|
|
if (ana_pwr & SGTL5000_LINEREG_D_POWERUP)
|
|
snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
|
|
SGTL5000_LINREG_SIMPLE_POWERUP,
|
|
0);
|
|
else
|
|
snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
|
|
SGTL5000_LINREG_SIMPLE_POWERUP |
|
|
SGTL5000_STARTUP_POWERUP,
|
|
0);
|
|
|
|
/*
|
|
* set ADC/DAC VAG to vdda / 2,
|
|
* should stay in range (0.8v, 1.575v)
|
|
*/
|
|
vag = vdda / 2;
|
|
if (vag <= SGTL5000_ANA_GND_BASE)
|
|
vag = 0;
|
|
else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP *
|
|
(SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT))
|
|
vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT;
|
|
else
|
|
vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP;
|
|
|
|
snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
|
|
SGTL5000_ANA_GND_MASK, vag << SGTL5000_ANA_GND_SHIFT);
|
|
|
|
/* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */
|
|
vag = vddio / 2;
|
|
if (vag <= SGTL5000_LINE_OUT_GND_BASE)
|
|
vag = 0;
|
|
else if (vag >= SGTL5000_LINE_OUT_GND_BASE +
|
|
SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX)
|
|
vag = SGTL5000_LINE_OUT_GND_MAX;
|
|
else
|
|
vag = (vag - SGTL5000_LINE_OUT_GND_BASE) /
|
|
SGTL5000_LINE_OUT_GND_STP;
|
|
|
|
snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
|
|
SGTL5000_LINE_OUT_CURRENT_MASK |
|
|
SGTL5000_LINE_OUT_GND_MASK,
|
|
vag << SGTL5000_LINE_OUT_GND_SHIFT |
|
|
SGTL5000_LINE_OUT_CURRENT_360u <<
|
|
SGTL5000_LINE_OUT_CURRENT_SHIFT);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sgtl5000_replace_vddd_with_ldo(struct snd_soc_codec *codec)
|
|
{
|
|
struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
|
|
int ret;
|
|
|
|
/* set internal ldo to 1.2v */
|
|
ret = ldo_regulator_register(codec, &ldo_init_data, LDO_VOLTAGE);
|
|
if (ret) {
|
|
dev_err(codec->dev,
|
|
"Failed to register vddd internal supplies: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
sgtl5000->supplies[VDDD].supply = LDO_CONSUMER_NAME;
|
|
|
|
ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies),
|
|
sgtl5000->supplies);
|
|
|
|
if (ret) {
|
|
ldo_regulator_remove(codec);
|
|
dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
dev_info(codec->dev, "Using internal LDO instead of VDDD\n");
|
|
return 0;
|
|
}
|
|
|
|
static int sgtl5000_enable_regulators(struct snd_soc_codec *codec)
|
|
{
|
|
int reg;
|
|
int ret;
|
|
int rev;
|
|
int i;
|
|
int external_vddd = 0;
|
|
struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
|
|
|
|
for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++)
|
|
sgtl5000->supplies[i].supply = supply_names[i];
|
|
|
|
ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies),
|
|
sgtl5000->supplies);
|
|
if (!ret)
|
|
external_vddd = 1;
|
|
else {
|
|
ret = sgtl5000_replace_vddd_with_ldo(codec);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies),
|
|
sgtl5000->supplies);
|
|
if (ret)
|
|
goto err_regulator_free;
|
|
|
|
/* wait for all power rails bring up */
|
|
udelay(10);
|
|
|
|
/*
|
|
* workaround for revision 0x11 and later,
|
|
* roll back to use internal LDO
|
|
*/
|
|
|
|
ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, ®);
|
|
if (ret)
|
|
goto err_regulator_disable;
|
|
|
|
rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT;
|
|
|
|
if (external_vddd && rev >= 0x11) {
|
|
/* disable all regulator first */
|
|
regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
|
|
sgtl5000->supplies);
|
|
/* free VDDD regulator */
|
|
regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
|
|
sgtl5000->supplies);
|
|
|
|
ret = sgtl5000_replace_vddd_with_ldo(codec);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies),
|
|
sgtl5000->supplies);
|
|
if (ret)
|
|
goto err_regulator_free;
|
|
|
|
/* wait for all power rails bring up */
|
|
udelay(10);
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_regulator_disable:
|
|
regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
|
|
sgtl5000->supplies);
|
|
err_regulator_free:
|
|
regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
|
|
sgtl5000->supplies);
|
|
if (external_vddd)
|
|
ldo_regulator_remove(codec);
|
|
return ret;
|
|
|
|
}
|
|
|
|
static int sgtl5000_probe(struct snd_soc_codec *codec)
|
|
{
|
|
int ret;
|
|
struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
|
|
|
|
/* setup i2c data ops */
|
|
codec->control_data = sgtl5000->regmap;
|
|
ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
|
|
if (ret < 0) {
|
|
dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = sgtl5000_enable_regulators(codec);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* power up sgtl5000 */
|
|
ret = sgtl5000_set_power_regs(codec);
|
|
if (ret)
|
|
goto err;
|
|
|
|
/* enable small pop, introduce 400ms delay in turning off */
|
|
snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
|
|
SGTL5000_SMALL_POP,
|
|
SGTL5000_SMALL_POP);
|
|
|
|
/* disable short cut detector */
|
|
snd_soc_write(codec, SGTL5000_CHIP_SHORT_CTRL, 0);
|
|
|
|
/*
|
|
* set i2s as default input of sound switch
|
|
* TODO: add sound switch to control and dapm widge.
|
|
*/
|
|
snd_soc_write(codec, SGTL5000_CHIP_SSS_CTRL,
|
|
SGTL5000_DAC_SEL_I2S_IN << SGTL5000_DAC_SEL_SHIFT);
|
|
snd_soc_write(codec, SGTL5000_CHIP_DIG_POWER,
|
|
SGTL5000_ADC_EN | SGTL5000_DAC_EN);
|
|
|
|
/* enable dac volume ramp by default */
|
|
snd_soc_write(codec, SGTL5000_CHIP_ADCDAC_CTRL,
|
|
SGTL5000_DAC_VOL_RAMP_EN |
|
|
SGTL5000_DAC_MUTE_RIGHT |
|
|
SGTL5000_DAC_MUTE_LEFT);
|
|
|
|
snd_soc_write(codec, SGTL5000_CHIP_PAD_STRENGTH, 0x015f);
|
|
|
|
snd_soc_write(codec, SGTL5000_CHIP_ANA_CTRL,
|
|
SGTL5000_HP_ZCD_EN |
|
|
SGTL5000_ADC_ZCD_EN);
|
|
|
|
snd_soc_write(codec, SGTL5000_CHIP_MIC_CTRL, 2);
|
|
|
|
/*
|
|
* disable DAP
|
|
* TODO:
|
|
* Enable DAP in kcontrol and dapm.
|
|
*/
|
|
snd_soc_write(codec, SGTL5000_DAP_CTRL, 0);
|
|
|
|
/* leading to standby state */
|
|
ret = sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
|
|
if (ret)
|
|
goto err;
|
|
|
|
return 0;
|
|
|
|
err:
|
|
regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
|
|
sgtl5000->supplies);
|
|
regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
|
|
sgtl5000->supplies);
|
|
ldo_regulator_remove(codec);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int sgtl5000_remove(struct snd_soc_codec *codec)
|
|
{
|
|
struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
|
|
|
|
sgtl5000_set_bias_level(codec, SND_SOC_BIAS_OFF);
|
|
|
|
regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
|
|
sgtl5000->supplies);
|
|
regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
|
|
sgtl5000->supplies);
|
|
ldo_regulator_remove(codec);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct snd_soc_codec_driver sgtl5000_driver = {
|
|
.probe = sgtl5000_probe,
|
|
.remove = sgtl5000_remove,
|
|
.suspend = sgtl5000_suspend,
|
|
.resume = sgtl5000_resume,
|
|
.set_bias_level = sgtl5000_set_bias_level,
|
|
.controls = sgtl5000_snd_controls,
|
|
.num_controls = ARRAY_SIZE(sgtl5000_snd_controls),
|
|
.dapm_widgets = sgtl5000_dapm_widgets,
|
|
.num_dapm_widgets = ARRAY_SIZE(sgtl5000_dapm_widgets),
|
|
.dapm_routes = sgtl5000_dapm_routes,
|
|
.num_dapm_routes = ARRAY_SIZE(sgtl5000_dapm_routes),
|
|
};
|
|
|
|
static const struct regmap_config sgtl5000_regmap = {
|
|
.reg_bits = 16,
|
|
.val_bits = 16,
|
|
.reg_stride = 2,
|
|
|
|
.max_register = SGTL5000_MAX_REG_OFFSET,
|
|
.volatile_reg = sgtl5000_volatile,
|
|
.readable_reg = sgtl5000_readable,
|
|
|
|
.cache_type = REGCACHE_RBTREE,
|
|
.reg_defaults = sgtl5000_reg_defaults,
|
|
.num_reg_defaults = ARRAY_SIZE(sgtl5000_reg_defaults),
|
|
};
|
|
|
|
/*
|
|
* Write all the default values from sgtl5000_reg_defaults[] array into the
|
|
* sgtl5000 registers, to make sure we always start with the sane registers
|
|
* values as stated in the datasheet.
|
|
*
|
|
* Since sgtl5000 does not have a reset line, nor a reset command in software,
|
|
* we follow this approach to guarantee we always start from the default values
|
|
* and avoid problems like, not being able to probe after an audio playback
|
|
* followed by a system reset or a 'reboot' command in Linux
|
|
*/
|
|
static int sgtl5000_fill_defaults(struct sgtl5000_priv *sgtl5000)
|
|
{
|
|
int i, ret, val, index;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(sgtl5000_reg_defaults); i++) {
|
|
val = sgtl5000_reg_defaults[i].def;
|
|
index = sgtl5000_reg_defaults[i].reg;
|
|
ret = regmap_write(sgtl5000->regmap, index, val);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sgtl5000_i2c_probe(struct i2c_client *client,
|
|
const struct i2c_device_id *id)
|
|
{
|
|
struct sgtl5000_priv *sgtl5000;
|
|
int ret, reg, rev;
|
|
|
|
sgtl5000 = devm_kzalloc(&client->dev, sizeof(struct sgtl5000_priv),
|
|
GFP_KERNEL);
|
|
if (!sgtl5000)
|
|
return -ENOMEM;
|
|
|
|
sgtl5000->regmap = devm_regmap_init_i2c(client, &sgtl5000_regmap);
|
|
if (IS_ERR(sgtl5000->regmap)) {
|
|
ret = PTR_ERR(sgtl5000->regmap);
|
|
dev_err(&client->dev, "Failed to allocate regmap: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
sgtl5000->mclk = devm_clk_get(&client->dev, NULL);
|
|
if (IS_ERR(sgtl5000->mclk)) {
|
|
ret = PTR_ERR(sgtl5000->mclk);
|
|
dev_err(&client->dev, "Failed to get mclock: %d\n", ret);
|
|
/* Defer the probe to see if the clk will be provided later */
|
|
if (ret == -ENOENT)
|
|
return -EPROBE_DEFER;
|
|
return ret;
|
|
}
|
|
|
|
ret = clk_prepare_enable(sgtl5000->mclk);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* read chip information */
|
|
ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, ®);
|
|
if (ret)
|
|
goto disable_clk;
|
|
|
|
if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) !=
|
|
SGTL5000_PARTID_PART_ID) {
|
|
dev_err(&client->dev,
|
|
"Device with ID register %x is not a sgtl5000\n", reg);
|
|
ret = -ENODEV;
|
|
goto disable_clk;
|
|
}
|
|
|
|
rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT;
|
|
dev_info(&client->dev, "sgtl5000 revision 0x%x\n", rev);
|
|
|
|
i2c_set_clientdata(client, sgtl5000);
|
|
|
|
/* Ensure sgtl5000 will start with sane register values */
|
|
ret = sgtl5000_fill_defaults(sgtl5000);
|
|
if (ret)
|
|
goto disable_clk;
|
|
|
|
ret = snd_soc_register_codec(&client->dev,
|
|
&sgtl5000_driver, &sgtl5000_dai, 1);
|
|
if (ret)
|
|
goto disable_clk;
|
|
|
|
return 0;
|
|
|
|
disable_clk:
|
|
clk_disable_unprepare(sgtl5000->mclk);
|
|
return ret;
|
|
}
|
|
|
|
static int sgtl5000_i2c_remove(struct i2c_client *client)
|
|
{
|
|
struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
|
|
|
|
snd_soc_unregister_codec(&client->dev);
|
|
clk_disable_unprepare(sgtl5000->mclk);
|
|
return 0;
|
|
}
|
|
|
|
static const struct i2c_device_id sgtl5000_id[] = {
|
|
{"sgtl5000", 0},
|
|
{},
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(i2c, sgtl5000_id);
|
|
|
|
static const struct of_device_id sgtl5000_dt_ids[] = {
|
|
{ .compatible = "fsl,sgtl5000", },
|
|
{ /* sentinel */ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, sgtl5000_dt_ids);
|
|
|
|
static struct i2c_driver sgtl5000_i2c_driver = {
|
|
.driver = {
|
|
.name = "sgtl5000",
|
|
.owner = THIS_MODULE,
|
|
.of_match_table = sgtl5000_dt_ids,
|
|
},
|
|
.probe = sgtl5000_i2c_probe,
|
|
.remove = sgtl5000_i2c_remove,
|
|
.id_table = sgtl5000_id,
|
|
};
|
|
|
|
module_i2c_driver(sgtl5000_i2c_driver);
|
|
|
|
MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver");
|
|
MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>");
|
|
MODULE_LICENSE("GPL");
|