fe78118c46
smc registers are access indirectly via the main mmio aperture, so there may be problems with concurrent access. This adds a spinlock to protect access to this register space. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
207 lines
6.6 KiB
C
207 lines
6.6 KiB
C
/*
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* Copyright 2011 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __RV770_SMC_H__
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#define __RV770_SMC_H__
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#include "ppsmc.h"
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#pragma pack(push, 1)
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#define RV770_SMC_TABLE_ADDRESS 0xB000
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#define RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 3
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struct RV770_SMC_SCLK_VALUE
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{
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uint32_t vCG_SPLL_FUNC_CNTL;
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uint32_t vCG_SPLL_FUNC_CNTL_2;
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uint32_t vCG_SPLL_FUNC_CNTL_3;
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uint32_t vCG_SPLL_SPREAD_SPECTRUM;
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uint32_t vCG_SPLL_SPREAD_SPECTRUM_2;
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uint32_t sclk_value;
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};
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typedef struct RV770_SMC_SCLK_VALUE RV770_SMC_SCLK_VALUE;
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struct RV770_SMC_MCLK_VALUE
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{
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uint32_t vMPLL_AD_FUNC_CNTL;
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uint32_t vMPLL_AD_FUNC_CNTL_2;
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uint32_t vMPLL_DQ_FUNC_CNTL;
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uint32_t vMPLL_DQ_FUNC_CNTL_2;
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uint32_t vMCLK_PWRMGT_CNTL;
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uint32_t vDLL_CNTL;
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uint32_t vMPLL_SS;
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uint32_t vMPLL_SS2;
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uint32_t mclk_value;
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};
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typedef struct RV770_SMC_MCLK_VALUE RV770_SMC_MCLK_VALUE;
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struct RV730_SMC_MCLK_VALUE
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{
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uint32_t vMCLK_PWRMGT_CNTL;
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uint32_t vDLL_CNTL;
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uint32_t vMPLL_FUNC_CNTL;
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uint32_t vMPLL_FUNC_CNTL2;
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uint32_t vMPLL_FUNC_CNTL3;
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uint32_t vMPLL_SS;
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uint32_t vMPLL_SS2;
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uint32_t mclk_value;
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};
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typedef struct RV730_SMC_MCLK_VALUE RV730_SMC_MCLK_VALUE;
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struct RV770_SMC_VOLTAGE_VALUE
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{
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uint16_t value;
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uint8_t index;
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uint8_t padding;
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};
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typedef struct RV770_SMC_VOLTAGE_VALUE RV770_SMC_VOLTAGE_VALUE;
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union RV7XX_SMC_MCLK_VALUE
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{
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RV770_SMC_MCLK_VALUE mclk770;
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RV730_SMC_MCLK_VALUE mclk730;
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};
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typedef union RV7XX_SMC_MCLK_VALUE RV7XX_SMC_MCLK_VALUE, *LPRV7XX_SMC_MCLK_VALUE;
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struct RV770_SMC_HW_PERFORMANCE_LEVEL
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{
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uint8_t arbValue;
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union{
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uint8_t seqValue;
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uint8_t ACIndex;
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};
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uint8_t displayWatermark;
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uint8_t gen2PCIE;
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uint8_t gen2XSP;
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uint8_t backbias;
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uint8_t strobeMode;
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uint8_t mcFlags;
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uint32_t aT;
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uint32_t bSP;
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RV770_SMC_SCLK_VALUE sclk;
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RV7XX_SMC_MCLK_VALUE mclk;
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RV770_SMC_VOLTAGE_VALUE vddc;
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RV770_SMC_VOLTAGE_VALUE mvdd;
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RV770_SMC_VOLTAGE_VALUE vddci;
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uint8_t reserved1;
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uint8_t reserved2;
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uint8_t stateFlags;
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uint8_t padding;
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};
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#define SMC_STROBE_RATIO 0x0F
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#define SMC_STROBE_ENABLE 0x10
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#define SMC_MC_EDC_RD_FLAG 0x01
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#define SMC_MC_EDC_WR_FLAG 0x02
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#define SMC_MC_RTT_ENABLE 0x04
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#define SMC_MC_STUTTER_EN 0x08
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typedef struct RV770_SMC_HW_PERFORMANCE_LEVEL RV770_SMC_HW_PERFORMANCE_LEVEL;
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struct RV770_SMC_SWSTATE
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{
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uint8_t flags;
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uint8_t padding1;
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uint8_t padding2;
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uint8_t padding3;
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RV770_SMC_HW_PERFORMANCE_LEVEL levels[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE];
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};
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typedef struct RV770_SMC_SWSTATE RV770_SMC_SWSTATE;
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#define RV770_SMC_VOLTAGEMASK_VDDC 0
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#define RV770_SMC_VOLTAGEMASK_MVDD 1
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#define RV770_SMC_VOLTAGEMASK_VDDCI 2
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#define RV770_SMC_VOLTAGEMASK_MAX 4
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struct RV770_SMC_VOLTAGEMASKTABLE
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{
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uint8_t highMask[RV770_SMC_VOLTAGEMASK_MAX];
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uint32_t lowMask[RV770_SMC_VOLTAGEMASK_MAX];
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};
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typedef struct RV770_SMC_VOLTAGEMASKTABLE RV770_SMC_VOLTAGEMASKTABLE;
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#define MAX_NO_VREG_STEPS 32
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struct RV770_SMC_STATETABLE
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{
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uint8_t thermalProtectType;
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uint8_t systemFlags;
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uint8_t maxVDDCIndexInPPTable;
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uint8_t extraFlags;
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uint8_t highSMIO[MAX_NO_VREG_STEPS];
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uint32_t lowSMIO[MAX_NO_VREG_STEPS];
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RV770_SMC_VOLTAGEMASKTABLE voltageMaskTable;
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RV770_SMC_SWSTATE initialState;
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RV770_SMC_SWSTATE ACPIState;
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RV770_SMC_SWSTATE driverState;
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RV770_SMC_SWSTATE ULVState;
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};
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typedef struct RV770_SMC_STATETABLE RV770_SMC_STATETABLE;
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#define PPSMC_STATEFLAG_AUTO_PULSE_SKIP 0x01
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#pragma pack(pop)
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#define RV770_SMC_SOFT_REGISTERS_START 0x104
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#define RV770_SMC_SOFT_REGISTER_mclk_chg_timeout 0x0
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#define RV770_SMC_SOFT_REGISTER_baby_step_timer 0x8
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#define RV770_SMC_SOFT_REGISTER_delay_bbias 0xC
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#define RV770_SMC_SOFT_REGISTER_delay_vreg 0x10
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#define RV770_SMC_SOFT_REGISTER_delay_acpi 0x2C
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#define RV770_SMC_SOFT_REGISTER_seq_index 0x64
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#define RV770_SMC_SOFT_REGISTER_mvdd_chg_time 0x68
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#define RV770_SMC_SOFT_REGISTER_mclk_switch_lim 0x78
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#define RV770_SMC_SOFT_REGISTER_mc_block_delay 0x90
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#define RV770_SMC_SOFT_REGISTER_uvd_enabled 0x9C
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#define RV770_SMC_SOFT_REGISTER_is_asic_lombok 0xA0
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int rv770_copy_bytes_to_smc(struct radeon_device *rdev,
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u16 smc_start_address, const u8 *src,
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u16 byte_count, u16 limit);
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void rv770_start_smc(struct radeon_device *rdev);
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void rv770_reset_smc(struct radeon_device *rdev);
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void rv770_stop_smc_clock(struct radeon_device *rdev);
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void rv770_start_smc_clock(struct radeon_device *rdev);
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bool rv770_is_smc_running(struct radeon_device *rdev);
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PPSMC_Result rv770_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg);
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PPSMC_Result rv770_wait_for_smc_inactive(struct radeon_device *rdev);
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int rv770_read_smc_sram_dword(struct radeon_device *rdev,
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u16 smc_address, u32 *value, u16 limit);
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int rv770_write_smc_sram_dword(struct radeon_device *rdev,
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u16 smc_address, u32 value, u16 limit);
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int rv770_load_smc_ucode(struct radeon_device *rdev,
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u16 limit);
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#endif
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