9d67006e6e
This adds dpm support for rs780/rs880 asics. This includes: - clockgating - dynamic engine clock scaling - dynamic voltage scaling set radeon.dpm=1 to enable it. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
109 lines
3.5 KiB
C
109 lines
3.5 KiB
C
/*
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* Copyright 2011 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __RS780_DPM_H__
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#define __RS780_DPM_H__
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enum rs780_vddc_level {
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RS780_VDDC_LEVEL_UNKNOWN = 0,
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RS780_VDDC_LEVEL_LOW = 1,
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RS780_VDDC_LEVEL_HIGH = 2,
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};
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struct igp_power_info {
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/* flags */
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bool invert_pwm_required;
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bool pwm_voltage_control;
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bool voltage_control;
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bool gfx_clock_gating;
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/* stored values */
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u32 system_config;
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u32 bootup_uma_clk;
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u16 max_voltage;
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u16 min_voltage;
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u16 boot_voltage;
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u16 inter_voltage_low;
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u16 inter_voltage_high;
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u16 num_of_cycles_in_period;
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/* variable */
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int crtc_id;
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int refresh_rate;
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};
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struct igp_ps {
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enum rs780_vddc_level min_voltage;
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enum rs780_vddc_level max_voltage;
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u32 sclk_low;
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u32 sclk_high;
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u32 flags;
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};
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#define RS780_CGFTV_DFLT 0x0303000f
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#define RS780_FBDIVTIMERVAL_DFLT 0x2710
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#define RS780_FVTHROTUTC0_DFLT 0x04010040
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#define RS780_FVTHROTUTC1_DFLT 0x04010040
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#define RS780_FVTHROTUTC2_DFLT 0x04010040
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#define RS780_FVTHROTUTC3_DFLT 0x04010040
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#define RS780_FVTHROTUTC4_DFLT 0x04010040
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#define RS780_FVTHROTDTC0_DFLT 0x04010040
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#define RS780_FVTHROTDTC1_DFLT 0x04010040
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#define RS780_FVTHROTDTC2_DFLT 0x04010040
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#define RS780_FVTHROTDTC3_DFLT 0x04010040
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#define RS780_FVTHROTDTC4_DFLT 0x04010040
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#define RS780_FVTHROTFBUSREG0_DFLT 0x00001001
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#define RS780_FVTHROTFBUSREG1_DFLT 0x00002002
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#define RS780_FVTHROTFBDSREG0_DFLT 0x00004001
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#define RS780_FVTHROTFBDSREG1_DFLT 0x00020010
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#define RS780_FVTHROTPWMUSREG0_DFLT 0x00002001
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#define RS780_FVTHROTPWMUSREG1_DFLT 0x00004003
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#define RS780_FVTHROTPWMDSREG0_DFLT 0x00002001
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#define RS780_FVTHROTPWMDSREG1_DFLT 0x00004003
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#define RS780_FVTHROTPWMFBDIVRANGEREG0_DFLT 0x37
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#define RS780_FVTHROTPWMFBDIVRANGEREG1_DFLT 0x4b
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#define RS780_FVTHROTPWMFBDIVRANGEREG2_DFLT 0x8b
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#define RS780D_FVTHROTPWMFBDIVRANGEREG0_DFLT 0x8b
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#define RS780D_FVTHROTPWMFBDIVRANGEREG1_DFLT 0x8c
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#define RS780D_FVTHROTPWMFBDIVRANGEREG2_DFLT 0xb5
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#define RS880D_FVTHROTPWMFBDIVRANGEREG0_DFLT 0x8d
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#define RS880D_FVTHROTPWMFBDIVRANGEREG1_DFLT 0x8e
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#define RS880D_FVTHROTPWMFBDIVRANGEREG2_DFLT 0xBa
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#define RS780_FVTHROTPWMRANGE0_GPIO_DFLT 0x1a
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#define RS780_FVTHROTPWMRANGE1_GPIO_DFLT 0x1a
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#define RS780_FVTHROTPWMRANGE2_GPIO_DFLT 0x0
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#define RS780_FVTHROTPWMRANGE3_GPIO_DFLT 0x0
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#define RS780_SLOWCLKFEEDBACKDIV_DFLT 110
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#define RS780_CGCLKGATING_DFLT 0x0000E204
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#define RS780_DEFAULT_VCLK_FREQ 53300 /* 10 khz */
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#define RS780_DEFAULT_DCLK_FREQ 40000 /* 10 khz */
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#endif
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