a53c8fab3f
Remove the file name from the comment at top of many files. In most cases the file name was wrong anyway, so it's rather pointless. Also unify the IBM copyright statement. We did have a lot of sightly different statements and wanted to change them one after another whenever a file gets touched. However that never happened. Instead people start to take the old/"wrong" statements to use as a template for new files. So unify all of them in one go. Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
155 lines
4.8 KiB
ArmAsm
155 lines
4.8 KiB
ArmAsm
/*
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* Copyright IBM Corp 2000, 2011
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* Author(s): Holger Smolinski <Holger.Smolinski@de.ibm.com>,
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* Denis Joseph Barrow,
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*/
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#include <linux/linkage.h>
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#include <asm/asm-offsets.h>
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#include <asm/sigp.h>
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#
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# store_status
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#
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# Prerequisites to run this function:
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# - Prefix register is set to zero
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# - Original prefix register is stored in "dump_prefix_page"
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# - Lowcore protection is off
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#
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ENTRY(store_status)
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/* Save register one and load save area base */
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stg %r1,__LC_SAVE_AREA_RESTART
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lghi %r1,SAVE_AREA_BASE
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/* General purpose registers */
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stmg %r0,%r15,__LC_GPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
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lg %r2,__LC_SAVE_AREA_RESTART
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stg %r2,__LC_GPREGS_SAVE_AREA-SAVE_AREA_BASE+8(%r1)
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/* Control registers */
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stctg %c0,%c15,__LC_CREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
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/* Access registers */
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stam %a0,%a15,__LC_AREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
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/* Floating point registers */
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std %f0, 0x00 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
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std %f1, 0x08 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
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std %f2, 0x10 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
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std %f3, 0x18 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
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std %f4, 0x20 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
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std %f5, 0x28 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
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std %f6, 0x30 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
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std %f7, 0x38 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
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std %f8, 0x40 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
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std %f9, 0x48 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
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std %f10,0x50 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
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std %f11,0x58 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
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std %f12,0x60 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
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std %f13,0x68 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
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std %f14,0x70 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
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std %f15,0x78 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
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/* Floating point control register */
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stfpc __LC_FP_CREG_SAVE_AREA-SAVE_AREA_BASE(%r1)
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/* CPU timer */
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stpt __LC_CPU_TIMER_SAVE_AREA-SAVE_AREA_BASE(%r1)
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/* Saved prefix register */
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larl %r2,dump_prefix_page
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mvc __LC_PREFIX_SAVE_AREA-SAVE_AREA_BASE(4,%r1),0(%r2)
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/* Clock comparator - seven bytes */
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larl %r2,.Lclkcmp
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stckc 0(%r2)
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mvc __LC_CLOCK_COMP_SAVE_AREA-SAVE_AREA_BASE + 1(7,%r1),1(%r2)
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/* Program status word */
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epsw %r2,%r3
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st %r2,__LC_PSW_SAVE_AREA-SAVE_AREA_BASE + 0(%r1)
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st %r3,__LC_PSW_SAVE_AREA-SAVE_AREA_BASE + 4(%r1)
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larl %r2,store_status
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stg %r2,__LC_PSW_SAVE_AREA-SAVE_AREA_BASE + 8(%r1)
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br %r14
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.section .bss
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.align 8
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.Lclkcmp: .quad 0x0000000000000000
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.previous
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#
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# do_reipl_asm
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# Parameter: r2 = schid of reipl device
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#
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ENTRY(do_reipl_asm)
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basr %r13,0
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.Lpg0: lpswe .Lnewpsw-.Lpg0(%r13)
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.Lpg1: brasl %r14,store_status
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lctlg %c6,%c6,.Lall-.Lpg0(%r13)
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lgr %r1,%r2
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mvc __LC_PGM_NEW_PSW(16),.Lpcnew-.Lpg0(%r13)
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stsch .Lschib-.Lpg0(%r13)
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oi .Lschib+5-.Lpg0(%r13),0x84
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.Lecs: xi .Lschib+27-.Lpg0(%r13),0x01
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msch .Lschib-.Lpg0(%r13)
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lghi %r0,5
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.Lssch: ssch .Liplorb-.Lpg0(%r13)
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jz .L001
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brct %r0,.Lssch
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bas %r14,.Ldisab-.Lpg0(%r13)
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.L001: mvc __LC_IO_NEW_PSW(16),.Lionew-.Lpg0(%r13)
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.Ltpi: lpswe .Lwaitpsw-.Lpg0(%r13)
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.Lcont: c %r1,__LC_SUBCHANNEL_ID
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jnz .Ltpi
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clc __LC_IO_INT_PARM(4),.Liplorb-.Lpg0(%r13)
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jnz .Ltpi
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tsch .Liplirb-.Lpg0(%r13)
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tm .Liplirb+9-.Lpg0(%r13),0xbf
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jz .L002
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bas %r14,.Ldisab-.Lpg0(%r13)
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.L002: tm .Liplirb+8-.Lpg0(%r13),0xf3
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jz .L003
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bas %r14,.Ldisab-.Lpg0(%r13)
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.L003: st %r1,__LC_SUBCHANNEL_ID
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lhi %r1,0 # mode 0 = esa
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slr %r0,%r0 # set cpuid to zero
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sigp %r1,%r0,SIGP_SET_ARCHITECTURE # switch to esa mode
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lpsw 0
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.Ldisab: sll %r14,1
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srl %r14,1 # need to kill hi bit to avoid specification exceptions.
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st %r14,.Ldispsw+12-.Lpg0(%r13)
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lpswe .Ldispsw-.Lpg0(%r13)
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.align 8
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.Lall: .quad 0x00000000ff000000
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.align 16
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/*
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* These addresses have to be 31 bit otherwise
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* the sigp will throw a specifcation exception
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* when switching to ESA mode as bit 31 be set
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* in the ESA psw.
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* Bit 31 of the addresses has to be 0 for the
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* 31bit lpswe instruction a fact they appear to have
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* omitted from the pop.
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*/
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.Lnewpsw: .quad 0x0000000080000000
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.quad .Lpg1
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.Lpcnew: .quad 0x0000000080000000
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.quad .Lecs
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.Lionew: .quad 0x0000000080000000
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.quad .Lcont
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.Lwaitpsw: .quad 0x0202000080000000
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.quad .Ltpi
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.Ldispsw: .quad 0x0002000080000000
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.quad 0x0000000000000000
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.Liplccws: .long 0x02000000,0x60000018
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.long 0x08000008,0x20000001
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.Liplorb: .long 0x0049504c,0x0040ff80
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.long 0x00000000+.Liplccws
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.Lschib: .long 0x00000000,0x00000000
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.long 0x00000000,0x00000000
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.long 0x00000000,0x00000000
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.long 0x00000000,0x00000000
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.long 0x00000000,0x00000000
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.long 0x00000000,0x00000000
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.Liplirb: .long 0x00000000,0x00000000
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.long 0x00000000,0x00000000
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.long 0x00000000,0x00000000
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.long 0x00000000,0x00000000
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.long 0x00000000,0x00000000
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.long 0x00000000,0x00000000
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.long 0x00000000,0x00000000
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.long 0x00000000,0x00000000
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