76968ad2ea
When we set the sun4u version of the PTE execute bit, it's: or REG, _PAGE_EXEC_4U, REG _PAGE_EXEC_4U is 0x1000, unfortunately the immedate field of the 'or' instruction is a signed 13-bit value. So the above actually assembles into: or REG, -4096, REG completely corrupting the final PTE value. Set it with a: sethi %hi(_PAGE_EXEC_4U), TMP or REG, TMP, REG sequence instead. This fixes "git gc" crashes on sun4u machines. Reported-by: Meelis Roos <mroos@linux.ee> Signed-off-by: David S. Miller <davem@davemloft.net>
364 lines
12 KiB
C
364 lines
12 KiB
C
#ifndef _SPARC64_TSB_H
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#define _SPARC64_TSB_H
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/* The sparc64 TSB is similar to the powerpc hashtables. It's a
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* power-of-2 sized table of TAG/PTE pairs. The cpu precomputes
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* pointers into this table for 8K and 64K page sizes, and also a
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* comparison TAG based upon the virtual address and context which
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* faults.
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*
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* TLB miss trap handler software does the actual lookup via something
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* of the form:
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*
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* ldxa [%g0] ASI_{D,I}MMU_TSB_8KB_PTR, %g1
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* ldxa [%g0] ASI_{D,I}MMU, %g6
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* sllx %g6, 22, %g6
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* srlx %g6, 22, %g6
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* ldda [%g1] ASI_NUCLEUS_QUAD_LDD, %g4
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* cmp %g4, %g6
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* bne,pn %xcc, tsb_miss_{d,i}tlb
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* mov FAULT_CODE_{D,I}TLB, %g3
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* stxa %g5, [%g0] ASI_{D,I}TLB_DATA_IN
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* retry
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*
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*
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* Each 16-byte slot of the TSB is the 8-byte tag and then the 8-byte
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* PTE. The TAG is of the same layout as the TLB TAG TARGET mmu
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* register which is:
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*
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* -------------------------------------------------
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* | - | CONTEXT | - | VADDR bits 63:22 |
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* -------------------------------------------------
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* 63 61 60 48 47 42 41 0
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*
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* But actually, since we use per-mm TSB's, we zero out the CONTEXT
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* field.
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*
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* Like the powerpc hashtables we need to use locking in order to
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* synchronize while we update the entries. PTE updates need locking
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* as well.
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*
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* We need to carefully choose a lock bits for the TSB entry. We
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* choose to use bit 47 in the tag. Also, since we never map anything
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* at page zero in context zero, we use zero as an invalid tag entry.
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* When the lock bit is set, this forces a tag comparison failure.
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*/
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#define TSB_TAG_LOCK_BIT 47
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#define TSB_TAG_LOCK_HIGH (1 << (TSB_TAG_LOCK_BIT - 32))
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#define TSB_TAG_INVALID_BIT 46
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#define TSB_TAG_INVALID_HIGH (1 << (TSB_TAG_INVALID_BIT - 32))
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/* Some cpus support physical address quad loads. We want to use
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* those if possible so we don't need to hard-lock the TSB mapping
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* into the TLB. We encode some instruction patching in order to
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* support this.
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*
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* The kernel TSB is locked into the TLB by virtue of being in the
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* kernel image, so we don't play these games for swapper_tsb access.
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*/
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#ifndef __ASSEMBLY__
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struct tsb_ldquad_phys_patch_entry {
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unsigned int addr;
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unsigned int sun4u_insn;
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unsigned int sun4v_insn;
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};
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extern struct tsb_ldquad_phys_patch_entry __tsb_ldquad_phys_patch,
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__tsb_ldquad_phys_patch_end;
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struct tsb_phys_patch_entry {
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unsigned int addr;
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unsigned int insn;
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};
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extern struct tsb_phys_patch_entry __tsb_phys_patch, __tsb_phys_patch_end;
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#endif
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#define TSB_LOAD_QUAD(TSB, REG) \
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661: ldda [TSB] ASI_NUCLEUS_QUAD_LDD, REG; \
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.section .tsb_ldquad_phys_patch, "ax"; \
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.word 661b; \
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ldda [TSB] ASI_QUAD_LDD_PHYS, REG; \
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ldda [TSB] ASI_QUAD_LDD_PHYS_4V, REG; \
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.previous
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#define TSB_LOAD_TAG_HIGH(TSB, REG) \
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661: lduwa [TSB] ASI_N, REG; \
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.section .tsb_phys_patch, "ax"; \
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.word 661b; \
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lduwa [TSB] ASI_PHYS_USE_EC, REG; \
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.previous
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#define TSB_LOAD_TAG(TSB, REG) \
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661: ldxa [TSB] ASI_N, REG; \
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.section .tsb_phys_patch, "ax"; \
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.word 661b; \
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ldxa [TSB] ASI_PHYS_USE_EC, REG; \
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.previous
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#define TSB_CAS_TAG_HIGH(TSB, REG1, REG2) \
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661: casa [TSB] ASI_N, REG1, REG2; \
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.section .tsb_phys_patch, "ax"; \
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.word 661b; \
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casa [TSB] ASI_PHYS_USE_EC, REG1, REG2; \
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.previous
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#define TSB_CAS_TAG(TSB, REG1, REG2) \
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661: casxa [TSB] ASI_N, REG1, REG2; \
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.section .tsb_phys_patch, "ax"; \
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.word 661b; \
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casxa [TSB] ASI_PHYS_USE_EC, REG1, REG2; \
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.previous
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#define TSB_STORE(ADDR, VAL) \
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661: stxa VAL, [ADDR] ASI_N; \
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.section .tsb_phys_patch, "ax"; \
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.word 661b; \
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stxa VAL, [ADDR] ASI_PHYS_USE_EC; \
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.previous
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#define TSB_LOCK_TAG(TSB, REG1, REG2) \
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99: TSB_LOAD_TAG_HIGH(TSB, REG1); \
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sethi %hi(TSB_TAG_LOCK_HIGH), REG2;\
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andcc REG1, REG2, %g0; \
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bne,pn %icc, 99b; \
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nop; \
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TSB_CAS_TAG_HIGH(TSB, REG1, REG2); \
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cmp REG1, REG2; \
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bne,pn %icc, 99b; \
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nop; \
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#define TSB_WRITE(TSB, TTE, TAG) \
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add TSB, 0x8, TSB; \
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TSB_STORE(TSB, TTE); \
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sub TSB, 0x8, TSB; \
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TSB_STORE(TSB, TAG);
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/* Do a kernel page table walk. Leaves physical PTE pointer in
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* REG1. Jumps to FAIL_LABEL on early page table walk termination.
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* VADDR will not be clobbered, but REG2 will.
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*/
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#define KERN_PGTABLE_WALK(VADDR, REG1, REG2, FAIL_LABEL) \
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sethi %hi(swapper_pg_dir), REG1; \
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or REG1, %lo(swapper_pg_dir), REG1; \
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sllx VADDR, 64 - (PGDIR_SHIFT + PGDIR_BITS), REG2; \
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srlx REG2, 64 - PAGE_SHIFT, REG2; \
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andn REG2, 0x3, REG2; \
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lduw [REG1 + REG2], REG1; \
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brz,pn REG1, FAIL_LABEL; \
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sllx VADDR, 64 - (PMD_SHIFT + PMD_BITS), REG2; \
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srlx REG2, 64 - PAGE_SHIFT, REG2; \
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sllx REG1, PGD_PADDR_SHIFT, REG1; \
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andn REG2, 0x3, REG2; \
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lduwa [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
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brz,pn REG1, FAIL_LABEL; \
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sllx VADDR, 64 - PMD_SHIFT, REG2; \
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srlx REG2, 64 - (PAGE_SHIFT - 1), REG2; \
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sllx REG1, PMD_PADDR_SHIFT, REG1; \
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andn REG2, 0x7, REG2; \
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add REG1, REG2, REG1;
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/* These macros exists only to make the PMD translator below
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* easier to read. It hides the ELF section switch for the
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* sun4v code patching.
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*/
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#define OR_PTE_BIT_1INSN(REG, NAME) \
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661: or REG, _PAGE_##NAME##_4U, REG; \
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.section .sun4v_1insn_patch, "ax"; \
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.word 661b; \
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or REG, _PAGE_##NAME##_4V, REG; \
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.previous;
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#define OR_PTE_BIT_2INSN(REG, TMP, NAME) \
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661: sethi %hi(_PAGE_##NAME##_4U), TMP; \
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or REG, TMP, REG; \
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.section .sun4v_2insn_patch, "ax"; \
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.word 661b; \
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mov -1, TMP; \
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or REG, _PAGE_##NAME##_4V, REG; \
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.previous;
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/* Load into REG the PTE value for VALID, CACHE, and SZHUGE. */
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#define BUILD_PTE_VALID_SZHUGE_CACHE(REG) \
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661: sethi %uhi(_PAGE_VALID|_PAGE_SZHUGE_4U), REG; \
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.section .sun4v_1insn_patch, "ax"; \
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.word 661b; \
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sethi %uhi(_PAGE_VALID), REG; \
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.previous; \
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sllx REG, 32, REG; \
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661: or REG, _PAGE_CP_4U|_PAGE_CV_4U, REG; \
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.section .sun4v_1insn_patch, "ax"; \
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.word 661b; \
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or REG, _PAGE_CP_4V|_PAGE_CV_4V|_PAGE_SZHUGE_4V, REG; \
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.previous;
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/* PMD has been loaded into REG1, interpret the value, seeing
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* if it is a HUGE PMD or a normal one. If it is not valid
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* then jump to FAIL_LABEL. If it is a HUGE PMD, and it
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* translates to a valid PTE, branch to PTE_LABEL.
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*
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* We translate the PMD by hand, one bit at a time,
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* constructing the huge PTE.
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*
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* So we construct the PTE in REG2 as follows:
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*
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* 1) Extract the PMD PFN from REG1 and place it into REG2.
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*
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* 2) Translate PMD protection bits in REG1 into REG2, one bit
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* at a time using andcc tests on REG1 and OR's into REG2.
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*
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* Only two bits to be concerned with here, EXEC and WRITE.
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* Now REG1 is freed up and we can use it as a temporary.
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*
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* 3) Construct the VALID, CACHE, and page size PTE bits in
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* REG1, OR with REG2 to form final PTE.
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*/
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#ifdef CONFIG_TRANSPARENT_HUGEPAGE
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#define USER_PGTABLE_CHECK_PMD_HUGE(VADDR, REG1, REG2, FAIL_LABEL, PTE_LABEL) \
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brz,pn REG1, FAIL_LABEL; \
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andcc REG1, PMD_ISHUGE, %g0; \
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be,pt %xcc, 700f; \
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and REG1, PMD_HUGE_PRESENT|PMD_HUGE_ACCESSED, REG2; \
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cmp REG2, PMD_HUGE_PRESENT|PMD_HUGE_ACCESSED; \
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bne,pn %xcc, FAIL_LABEL; \
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andn REG1, PMD_HUGE_PROTBITS, REG2; \
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sllx REG2, PMD_PADDR_SHIFT, REG2; \
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/* REG2 now holds PFN << PAGE_SHIFT */ \
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andcc REG1, PMD_HUGE_WRITE, %g0; \
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bne,a,pt %xcc, 1f; \
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OR_PTE_BIT_1INSN(REG2, W); \
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1: andcc REG1, PMD_HUGE_EXEC, %g0; \
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be,pt %xcc, 1f; \
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nop; \
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OR_PTE_BIT_2INSN(REG2, REG1, EXEC); \
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/* REG1 can now be clobbered, build final PTE */ \
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1: BUILD_PTE_VALID_SZHUGE_CACHE(REG1); \
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ba,pt %xcc, PTE_LABEL; \
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or REG1, REG2, REG1; \
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700:
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#else
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#define USER_PGTABLE_CHECK_PMD_HUGE(VADDR, REG1, REG2, FAIL_LABEL, PTE_LABEL) \
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brz,pn REG1, FAIL_LABEL; \
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nop;
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#endif
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/* Do a user page table walk in MMU globals. Leaves final,
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* valid, PTE value in REG1. Jumps to FAIL_LABEL on early
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* page table walk termination or if the PTE is not valid.
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*
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* Physical base of page tables is in PHYS_PGD which will not
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* be modified.
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*
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* VADDR will not be clobbered, but REG1 and REG2 will.
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*/
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#define USER_PGTABLE_WALK_TL1(VADDR, PHYS_PGD, REG1, REG2, FAIL_LABEL) \
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sllx VADDR, 64 - (PGDIR_SHIFT + PGDIR_BITS), REG2; \
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srlx REG2, 64 - PAGE_SHIFT, REG2; \
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andn REG2, 0x3, REG2; \
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lduwa [PHYS_PGD + REG2] ASI_PHYS_USE_EC, REG1; \
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brz,pn REG1, FAIL_LABEL; \
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sllx VADDR, 64 - (PMD_SHIFT + PMD_BITS), REG2; \
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srlx REG2, 64 - PAGE_SHIFT, REG2; \
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sllx REG1, PGD_PADDR_SHIFT, REG1; \
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andn REG2, 0x3, REG2; \
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lduwa [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
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USER_PGTABLE_CHECK_PMD_HUGE(VADDR, REG1, REG2, FAIL_LABEL, 800f) \
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sllx VADDR, 64 - PMD_SHIFT, REG2; \
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srlx REG2, 64 - (PAGE_SHIFT - 1), REG2; \
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sllx REG1, PMD_PADDR_SHIFT, REG1; \
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andn REG2, 0x7, REG2; \
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add REG1, REG2, REG1; \
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ldxa [REG1] ASI_PHYS_USE_EC, REG1; \
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brgez,pn REG1, FAIL_LABEL; \
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nop; \
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800:
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/* Lookup a OBP mapping on VADDR in the prom_trans[] table at TL>0.
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* If no entry is found, FAIL_LABEL will be branched to. On success
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* the resulting PTE value will be left in REG1. VADDR is preserved
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* by this routine.
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*/
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#define OBP_TRANS_LOOKUP(VADDR, REG1, REG2, REG3, FAIL_LABEL) \
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sethi %hi(prom_trans), REG1; \
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or REG1, %lo(prom_trans), REG1; \
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97: ldx [REG1 + 0x00], REG2; \
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brz,pn REG2, FAIL_LABEL; \
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nop; \
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ldx [REG1 + 0x08], REG3; \
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add REG2, REG3, REG3; \
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cmp REG2, VADDR; \
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bgu,pt %xcc, 98f; \
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cmp VADDR, REG3; \
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bgeu,pt %xcc, 98f; \
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ldx [REG1 + 0x10], REG3; \
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sub VADDR, REG2, REG2; \
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ba,pt %xcc, 99f; \
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add REG3, REG2, REG1; \
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98: ba,pt %xcc, 97b; \
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add REG1, (3 * 8), REG1; \
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99:
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/* We use a 32K TSB for the whole kernel, this allows to
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* handle about 16MB of modules and vmalloc mappings without
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* incurring many hash conflicts.
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*/
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#define KERNEL_TSB_SIZE_BYTES (32 * 1024)
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#define KERNEL_TSB_NENTRIES \
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(KERNEL_TSB_SIZE_BYTES / 16)
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#define KERNEL_TSB4M_NENTRIES 4096
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#define KTSB_PHYS_SHIFT 15
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/* Do a kernel TSB lookup at tl>0 on VADDR+TAG, branch to OK_LABEL
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* on TSB hit. REG1, REG2, REG3, and REG4 are used as temporaries
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* and the found TTE will be left in REG1. REG3 and REG4 must
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* be an even/odd pair of registers.
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*
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* VADDR and TAG will be preserved and not clobbered by this macro.
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*/
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#define KERN_TSB_LOOKUP_TL1(VADDR, TAG, REG1, REG2, REG3, REG4, OK_LABEL) \
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661: sethi %hi(swapper_tsb), REG1; \
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or REG1, %lo(swapper_tsb), REG1; \
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.section .swapper_tsb_phys_patch, "ax"; \
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.word 661b; \
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.previous; \
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661: nop; \
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.section .tsb_ldquad_phys_patch, "ax"; \
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.word 661b; \
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sllx REG1, KTSB_PHYS_SHIFT, REG1; \
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sllx REG1, KTSB_PHYS_SHIFT, REG1; \
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.previous; \
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srlx VADDR, PAGE_SHIFT, REG2; \
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and REG2, (KERNEL_TSB_NENTRIES - 1), REG2; \
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sllx REG2, 4, REG2; \
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add REG1, REG2, REG2; \
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TSB_LOAD_QUAD(REG2, REG3); \
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cmp REG3, TAG; \
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be,a,pt %xcc, OK_LABEL; \
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mov REG4, REG1;
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#ifndef CONFIG_DEBUG_PAGEALLOC
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/* This version uses a trick, the TAG is already (VADDR >> 22) so
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* we can make use of that for the index computation.
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*/
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#define KERN_TSB4M_LOOKUP_TL1(TAG, REG1, REG2, REG3, REG4, OK_LABEL) \
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661: sethi %hi(swapper_4m_tsb), REG1; \
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or REG1, %lo(swapper_4m_tsb), REG1; \
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.section .swapper_4m_tsb_phys_patch, "ax"; \
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.word 661b; \
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.previous; \
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661: nop; \
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.section .tsb_ldquad_phys_patch, "ax"; \
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.word 661b; \
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sllx REG1, KTSB_PHYS_SHIFT, REG1; \
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sllx REG1, KTSB_PHYS_SHIFT, REG1; \
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.previous; \
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and TAG, (KERNEL_TSB4M_NENTRIES - 1), REG2; \
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sllx REG2, 4, REG2; \
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add REG1, REG2, REG2; \
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TSB_LOAD_QUAD(REG2, REG3); \
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cmp REG3, TAG; \
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be,a,pt %xcc, OK_LABEL; \
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mov REG4, REG1;
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#endif
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#endif /* !(_SPARC64_TSB_H) */
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