63a1909190
The new uapi framework splits kernel internal and user space exported bits of header files more cleanly. Adjust the ePAPR header accordingly. Signed-off-by: Alexander Graf <agraf@suse.de>
458 lines
14 KiB
C
458 lines
14 KiB
C
/*
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* ePAPR hcall interface
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*
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* Copyright 2008-2011 Freescale Semiconductor, Inc.
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*
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* Author: Timur Tabi <timur@freescale.com>
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*
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* This file is provided under a dual BSD/GPL license. When using or
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* redistributing this file, you may do so under either license.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* A "hypercall" is an "sc 1" instruction. This header file file provides C
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* wrapper functions for the ePAPR hypervisor interface. It is inteded
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* for use by Linux device drivers and other operating systems.
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*
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* The hypercalls are implemented as inline assembly, rather than assembly
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* language functions in a .S file, for optimization. It allows
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* the caller to issue the hypercall instruction directly, improving both
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* performance and memory footprint.
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*/
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#ifndef _EPAPR_HCALLS_H
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#define _EPAPR_HCALLS_H
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#include <uapi/asm/epapr_hcalls.h>
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#ifndef __ASSEMBLY__
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <asm/byteorder.h>
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/*
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* Hypercall register clobber list
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*
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* These macros are used to define the list of clobbered registers during a
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* hypercall. Technically, registers r0 and r3-r12 are always clobbered,
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* but the gcc inline assembly syntax does not allow us to specify registers
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* on the clobber list that are also on the input/output list. Therefore,
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* the lists of clobbered registers depends on the number of register
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* parmeters ("+r" and "=r") passed to the hypercall.
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*
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* Each assembly block should use one of the HCALL_CLOBBERSx macros. As a
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* general rule, 'x' is the number of parameters passed to the assembly
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* block *except* for r11.
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*
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* If you're not sure, just use the smallest value of 'x' that does not
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* generate a compilation error. Because these are static inline functions,
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* the compiler will only check the clobber list for a function if you
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* compile code that calls that function.
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*
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* r3 and r11 are not included in any clobbers list because they are always
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* listed as output registers.
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*
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* XER, CTR, and LR are currently listed as clobbers because it's uncertain
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* whether they will be clobbered.
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*
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* Note that r11 can be used as an output parameter.
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*
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* The "memory" clobber is only necessary for hcalls where the Hypervisor
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* will read or write guest memory. However, we add it to all hcalls because
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* the impact is minimal, and we want to ensure that it's present for the
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* hcalls that need it.
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*/
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/* List of common clobbered registers. Do not use this macro. */
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#define EV_HCALL_CLOBBERS "r0", "r12", "xer", "ctr", "lr", "cc", "memory"
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#define EV_HCALL_CLOBBERS8 EV_HCALL_CLOBBERS
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#define EV_HCALL_CLOBBERS7 EV_HCALL_CLOBBERS8, "r10"
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#define EV_HCALL_CLOBBERS6 EV_HCALL_CLOBBERS7, "r9"
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#define EV_HCALL_CLOBBERS5 EV_HCALL_CLOBBERS6, "r8"
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#define EV_HCALL_CLOBBERS4 EV_HCALL_CLOBBERS5, "r7"
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#define EV_HCALL_CLOBBERS3 EV_HCALL_CLOBBERS4, "r6"
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#define EV_HCALL_CLOBBERS2 EV_HCALL_CLOBBERS3, "r5"
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#define EV_HCALL_CLOBBERS1 EV_HCALL_CLOBBERS2, "r4"
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extern bool epapr_paravirt_enabled;
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extern u32 epapr_hypercall_start[];
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/*
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* We use "uintptr_t" to define a register because it's guaranteed to be a
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* 32-bit integer on a 32-bit platform, and a 64-bit integer on a 64-bit
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* platform.
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*
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* All registers are either input/output or output only. Registers that are
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* initialized before making the hypercall are input/output. All
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* input/output registers are represented with "+r". Output-only registers
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* are represented with "=r". Do not specify any unused registers. The
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* clobber list will tell the compiler that the hypercall modifies those
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* registers, which is good enough.
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*/
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/**
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* ev_int_set_config - configure the specified interrupt
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* @interrupt: the interrupt number
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* @config: configuration for this interrupt
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* @priority: interrupt priority
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* @destination: destination CPU number
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*
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* Returns 0 for success, or an error code.
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*/
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static inline unsigned int ev_int_set_config(unsigned int interrupt,
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uint32_t config, unsigned int priority, uint32_t destination)
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{
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register uintptr_t r11 __asm__("r11");
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register uintptr_t r3 __asm__("r3");
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register uintptr_t r4 __asm__("r4");
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register uintptr_t r5 __asm__("r5");
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register uintptr_t r6 __asm__("r6");
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r11 = EV_HCALL_TOKEN(EV_INT_SET_CONFIG);
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r3 = interrupt;
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r4 = config;
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r5 = priority;
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r6 = destination;
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asm volatile("bl epapr_hypercall_start"
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: "+r" (r11), "+r" (r3), "+r" (r4), "+r" (r5), "+r" (r6)
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: : EV_HCALL_CLOBBERS4
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);
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return r3;
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}
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/**
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* ev_int_get_config - return the config of the specified interrupt
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* @interrupt: the interrupt number
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* @config: returned configuration for this interrupt
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* @priority: returned interrupt priority
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* @destination: returned destination CPU number
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*
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* Returns 0 for success, or an error code.
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*/
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static inline unsigned int ev_int_get_config(unsigned int interrupt,
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uint32_t *config, unsigned int *priority, uint32_t *destination)
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{
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register uintptr_t r11 __asm__("r11");
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register uintptr_t r3 __asm__("r3");
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register uintptr_t r4 __asm__("r4");
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register uintptr_t r5 __asm__("r5");
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register uintptr_t r6 __asm__("r6");
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r11 = EV_HCALL_TOKEN(EV_INT_GET_CONFIG);
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r3 = interrupt;
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asm volatile("bl epapr_hypercall_start"
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: "+r" (r11), "+r" (r3), "=r" (r4), "=r" (r5), "=r" (r6)
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: : EV_HCALL_CLOBBERS4
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);
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*config = r4;
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*priority = r5;
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*destination = r6;
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return r3;
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}
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/**
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* ev_int_set_mask - sets the mask for the specified interrupt source
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* @interrupt: the interrupt number
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* @mask: 0=enable interrupts, 1=disable interrupts
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*
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* Returns 0 for success, or an error code.
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*/
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static inline unsigned int ev_int_set_mask(unsigned int interrupt,
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unsigned int mask)
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{
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register uintptr_t r11 __asm__("r11");
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register uintptr_t r3 __asm__("r3");
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register uintptr_t r4 __asm__("r4");
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r11 = EV_HCALL_TOKEN(EV_INT_SET_MASK);
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r3 = interrupt;
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r4 = mask;
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asm volatile("bl epapr_hypercall_start"
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: "+r" (r11), "+r" (r3), "+r" (r4)
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: : EV_HCALL_CLOBBERS2
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);
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return r3;
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}
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/**
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* ev_int_get_mask - returns the mask for the specified interrupt source
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* @interrupt: the interrupt number
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* @mask: returned mask for this interrupt (0=enabled, 1=disabled)
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*
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* Returns 0 for success, or an error code.
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*/
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static inline unsigned int ev_int_get_mask(unsigned int interrupt,
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unsigned int *mask)
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{
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register uintptr_t r11 __asm__("r11");
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register uintptr_t r3 __asm__("r3");
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register uintptr_t r4 __asm__("r4");
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r11 = EV_HCALL_TOKEN(EV_INT_GET_MASK);
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r3 = interrupt;
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asm volatile("bl epapr_hypercall_start"
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: "+r" (r11), "+r" (r3), "=r" (r4)
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: : EV_HCALL_CLOBBERS2
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);
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*mask = r4;
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return r3;
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}
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/**
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* ev_int_eoi - signal the end of interrupt processing
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* @interrupt: the interrupt number
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*
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* This function signals the end of processing for the the specified
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* interrupt, which must be the interrupt currently in service. By
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* definition, this is also the highest-priority interrupt.
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*
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* Returns 0 for success, or an error code.
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*/
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static inline unsigned int ev_int_eoi(unsigned int interrupt)
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{
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register uintptr_t r11 __asm__("r11");
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register uintptr_t r3 __asm__("r3");
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r11 = EV_HCALL_TOKEN(EV_INT_EOI);
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r3 = interrupt;
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asm volatile("bl epapr_hypercall_start"
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: "+r" (r11), "+r" (r3)
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: : EV_HCALL_CLOBBERS1
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);
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return r3;
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}
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/**
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* ev_byte_channel_send - send characters to a byte stream
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* @handle: byte stream handle
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* @count: (input) num of chars to send, (output) num chars sent
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* @buffer: pointer to a 16-byte buffer
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*
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* @buffer must be at least 16 bytes long, because all 16 bytes will be
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* read from memory into registers, even if count < 16.
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*
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* Returns 0 for success, or an error code.
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*/
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static inline unsigned int ev_byte_channel_send(unsigned int handle,
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unsigned int *count, const char buffer[EV_BYTE_CHANNEL_MAX_BYTES])
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{
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register uintptr_t r11 __asm__("r11");
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register uintptr_t r3 __asm__("r3");
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register uintptr_t r4 __asm__("r4");
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register uintptr_t r5 __asm__("r5");
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register uintptr_t r6 __asm__("r6");
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register uintptr_t r7 __asm__("r7");
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register uintptr_t r8 __asm__("r8");
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const uint32_t *p = (const uint32_t *) buffer;
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r11 = EV_HCALL_TOKEN(EV_BYTE_CHANNEL_SEND);
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r3 = handle;
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r4 = *count;
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r5 = be32_to_cpu(p[0]);
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r6 = be32_to_cpu(p[1]);
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r7 = be32_to_cpu(p[2]);
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r8 = be32_to_cpu(p[3]);
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asm volatile("bl epapr_hypercall_start"
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: "+r" (r11), "+r" (r3),
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"+r" (r4), "+r" (r5), "+r" (r6), "+r" (r7), "+r" (r8)
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: : EV_HCALL_CLOBBERS6
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);
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*count = r4;
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return r3;
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}
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/**
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* ev_byte_channel_receive - fetch characters from a byte channel
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* @handle: byte channel handle
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* @count: (input) max num of chars to receive, (output) num chars received
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* @buffer: pointer to a 16-byte buffer
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*
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* The size of @buffer must be at least 16 bytes, even if you request fewer
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* than 16 characters, because we always write 16 bytes to @buffer. This is
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* for performance reasons.
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*
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* Returns 0 for success, or an error code.
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*/
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static inline unsigned int ev_byte_channel_receive(unsigned int handle,
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unsigned int *count, char buffer[EV_BYTE_CHANNEL_MAX_BYTES])
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{
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register uintptr_t r11 __asm__("r11");
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register uintptr_t r3 __asm__("r3");
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register uintptr_t r4 __asm__("r4");
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register uintptr_t r5 __asm__("r5");
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register uintptr_t r6 __asm__("r6");
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register uintptr_t r7 __asm__("r7");
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register uintptr_t r8 __asm__("r8");
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uint32_t *p = (uint32_t *) buffer;
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r11 = EV_HCALL_TOKEN(EV_BYTE_CHANNEL_RECEIVE);
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r3 = handle;
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r4 = *count;
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asm volatile("bl epapr_hypercall_start"
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: "+r" (r11), "+r" (r3), "+r" (r4),
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"=r" (r5), "=r" (r6), "=r" (r7), "=r" (r8)
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: : EV_HCALL_CLOBBERS6
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);
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*count = r4;
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p[0] = cpu_to_be32(r5);
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p[1] = cpu_to_be32(r6);
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p[2] = cpu_to_be32(r7);
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p[3] = cpu_to_be32(r8);
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return r3;
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}
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/**
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* ev_byte_channel_poll - returns the status of the byte channel buffers
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* @handle: byte channel handle
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* @rx_count: returned count of bytes in receive queue
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* @tx_count: returned count of free space in transmit queue
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*
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* This function reports the amount of data in the receive queue (i.e. the
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* number of bytes you can read), and the amount of free space in the transmit
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* queue (i.e. the number of bytes you can write).
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*
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* Returns 0 for success, or an error code.
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*/
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static inline unsigned int ev_byte_channel_poll(unsigned int handle,
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unsigned int *rx_count, unsigned int *tx_count)
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{
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register uintptr_t r11 __asm__("r11");
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register uintptr_t r3 __asm__("r3");
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register uintptr_t r4 __asm__("r4");
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register uintptr_t r5 __asm__("r5");
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r11 = EV_HCALL_TOKEN(EV_BYTE_CHANNEL_POLL);
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r3 = handle;
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asm volatile("bl epapr_hypercall_start"
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: "+r" (r11), "+r" (r3), "=r" (r4), "=r" (r5)
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: : EV_HCALL_CLOBBERS3
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);
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*rx_count = r4;
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*tx_count = r5;
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return r3;
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}
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/**
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* ev_int_iack - acknowledge an interrupt
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* @handle: handle to the target interrupt controller
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* @vector: returned interrupt vector
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*
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* If handle is zero, the function returns the next interrupt source
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* number to be handled irrespective of the hierarchy or cascading
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* of interrupt controllers. If non-zero, specifies a handle to the
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* interrupt controller that is the target of the acknowledge.
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*
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* Returns 0 for success, or an error code.
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*/
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static inline unsigned int ev_int_iack(unsigned int handle,
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unsigned int *vector)
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{
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register uintptr_t r11 __asm__("r11");
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register uintptr_t r3 __asm__("r3");
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register uintptr_t r4 __asm__("r4");
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r11 = EV_HCALL_TOKEN(EV_INT_IACK);
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r3 = handle;
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asm volatile("bl epapr_hypercall_start"
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: "+r" (r11), "+r" (r3), "=r" (r4)
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: : EV_HCALL_CLOBBERS2
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);
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*vector = r4;
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return r3;
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}
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/**
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* ev_doorbell_send - send a doorbell to another partition
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* @handle: doorbell send handle
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*
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* Returns 0 for success, or an error code.
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*/
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static inline unsigned int ev_doorbell_send(unsigned int handle)
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{
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register uintptr_t r11 __asm__("r11");
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register uintptr_t r3 __asm__("r3");
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r11 = EV_HCALL_TOKEN(EV_DOORBELL_SEND);
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r3 = handle;
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asm volatile("bl epapr_hypercall_start"
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: "+r" (r11), "+r" (r3)
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: : EV_HCALL_CLOBBERS1
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);
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return r3;
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}
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/**
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* ev_idle -- wait for next interrupt on this core
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*
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* Returns 0 for success, or an error code.
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*/
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static inline unsigned int ev_idle(void)
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{
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register uintptr_t r11 __asm__("r11");
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register uintptr_t r3 __asm__("r3");
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r11 = EV_HCALL_TOKEN(EV_IDLE);
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asm volatile("bl epapr_hypercall_start"
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: "+r" (r11), "=r" (r3)
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: : EV_HCALL_CLOBBERS1
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);
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return r3;
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}
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#endif /* !__ASSEMBLY__ */
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#endif /* _EPAPR_HCALLS_H */
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