1004165f34
The XLP USB controller appears as a device on the internal SoC PCIe
bus, the block has 2 EHCI blocks and 4 OHCI blocks. Change are to:
* Add files netlogic/xlp/usb-init.c and asm/netlogic/xlp-hal/usb.h
to initialize the USB controller and define PCI fixups. The PCI
fixups are to setup interrupts and DMA mask.
* Update include/asm/xlp-hal/{iomap.h,pic.h,xlp.h} to add interrupt
mapping for EHCI/OHCI interrupts.
Signed-off-by: Ganesan Ramalingam <ganesanr@netlogicmicro.com>
Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3756/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
64 lines
2.5 KiB
C
64 lines
2.5 KiB
C
/*
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* Copyright (c) 2003-2012 Broadcom Corporation
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* All Rights Reserved
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the Broadcom
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* license below:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __NLM_HAL_USB_H__
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#define __NLM_HAL_USB_H__
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#define USB_CTL_0 0x01
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#define USB_PHY_0 0x0A
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#define USB_PHY_RESET 0x01
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#define USB_PHY_PORT_RESET_0 0x10
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#define USB_PHY_PORT_RESET_1 0x20
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#define USB_CONTROLLER_RESET 0x01
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#define USB_INT_STATUS 0x0E
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#define USB_INT_EN 0x0F
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#define USB_PHY_INTERRUPT_EN 0x01
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#define USB_OHCI_INTERRUPT_EN 0x02
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#define USB_OHCI_INTERRUPT1_EN 0x04
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#define USB_OHCI_INTERRUPT2_EN 0x08
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#define USB_CTRL_INTERRUPT_EN 0x10
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#ifndef __ASSEMBLY__
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#define nlm_read_usb_reg(b, r) nlm_read_reg(b, r)
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#define nlm_write_usb_reg(b, r, v) nlm_write_reg(b, r, v)
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#define nlm_get_usb_pcibase(node, inst) \
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nlm_pcicfg_base(XLP_IO_USB_OFFSET(node, inst))
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#define nlm_get_usb_hcd_base(node, inst) \
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nlm_xkphys_map_pcibar0(nlm_get_usb_pcibase(node, inst))
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#define nlm_get_usb_regbase(node, inst) \
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(nlm_get_usb_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)
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#endif
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#endif /* __NLM_HAL_USB_H__ */
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