7034228792
Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
76 lines
2.8 KiB
C
76 lines
2.8 KiB
C
/*
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* Copyright (c) 2003-2012 Broadcom Corporation
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* All Rights Reserved
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the Broadcom
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* license below:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __NLM_HAL_PCIBUS_H__
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#define __NLM_HAL_PCIBUS_H__
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/* PCIE Memory and IO regions */
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#define PCIE_MEM_BASE 0xd0000000ULL
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#define PCIE_MEM_LIMIT 0xdfffffffULL
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#define PCIE_IO_BASE 0x14000000ULL
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#define PCIE_IO_LIMIT 0x15ffffffULL
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#define PCIE_BRIDGE_CMD 0x1
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#define PCIE_BRIDGE_MSI_CAP 0x14
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#define PCIE_BRIDGE_MSI_ADDRL 0x15
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#define PCIE_BRIDGE_MSI_ADDRH 0x16
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#define PCIE_BRIDGE_MSI_DATA 0x17
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/* XLP Global PCIE configuration space registers */
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#define PCIE_BYTE_SWAP_MEM_BASE 0x247
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#define PCIE_BYTE_SWAP_MEM_LIM 0x248
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#define PCIE_BYTE_SWAP_IO_BASE 0x249
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#define PCIE_BYTE_SWAP_IO_LIM 0x24A
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#define PCIE_MSI_STATUS 0x25A
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#define PCIE_MSI_EN 0x25B
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#define PCIE_INT_EN0 0x261
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/* PCIE_MSI_EN */
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#define PCIE_MSI_VECTOR_INT_EN 0xFFFFFFFF
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/* PCIE_INT_EN0 */
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#define PCIE_MSI_INT_EN (1 << 9)
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#ifndef __ASSEMBLY__
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#define nlm_read_pcie_reg(b, r) nlm_read_reg(b, r)
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#define nlm_write_pcie_reg(b, r, v) nlm_write_reg(b, r, v)
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#define nlm_get_pcie_base(node, inst) \
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nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node, inst))
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#define nlm_get_pcie_regbase(node, inst) \
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(nlm_get_pcie_base(node, inst) + XLP_IO_PCI_HDRSZ)
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int xlp_pcie_link_irt(int link);
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#endif
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#endif /* __NLM_HAL_PCIBUS_H__ */
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