7034228792
Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
101 lines
4.4 KiB
C
101 lines
4.4 KiB
C
/*
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* Locations of devices in the Calliope ASIC.
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*
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* Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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* Author: Ken Eppinett
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* David Schleef <ds@schleef.org>
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*
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* Description: Defines the platform resources for the SA settop.
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*/
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#include <linux/init.h>
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#include <asm/mach-powertv/asic.h>
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#define CALLIOPE_ADDR(x) (CALLIOPE_IO_BASE + (x))
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const struct register_map calliope_register_map __initconst = {
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.eic_slow0_strt_add = {.phys = CALLIOPE_ADDR(0x800000)},
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.eic_cfg_bits = {.phys = CALLIOPE_ADDR(0x800038)},
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.eic_ready_status = {.phys = CALLIOPE_ADDR(0x80004c)},
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.chipver3 = {.phys = CALLIOPE_ADDR(0xA00800)},
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.chipver2 = {.phys = CALLIOPE_ADDR(0xA00804)},
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.chipver1 = {.phys = CALLIOPE_ADDR(0xA00808)},
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.chipver0 = {.phys = CALLIOPE_ADDR(0xA0080c)},
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/* The registers of IRBlaster */
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.uart1_intstat = {.phys = CALLIOPE_ADDR(0xA01800)},
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.uart1_inten = {.phys = CALLIOPE_ADDR(0xA01804)},
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.uart1_config1 = {.phys = CALLIOPE_ADDR(0xA01808)},
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.uart1_config2 = {.phys = CALLIOPE_ADDR(0xA0180C)},
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.uart1_divisorhi = {.phys = CALLIOPE_ADDR(0xA01810)},
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.uart1_divisorlo = {.phys = CALLIOPE_ADDR(0xA01814)},
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.uart1_data = {.phys = CALLIOPE_ADDR(0xA01818)},
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.uart1_status = {.phys = CALLIOPE_ADDR(0xA0181C)},
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.int_stat_3 = {.phys = CALLIOPE_ADDR(0xA02800)},
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.int_stat_2 = {.phys = CALLIOPE_ADDR(0xA02804)},
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.int_stat_1 = {.phys = CALLIOPE_ADDR(0xA02808)},
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.int_stat_0 = {.phys = CALLIOPE_ADDR(0xA0280c)},
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.int_config = {.phys = CALLIOPE_ADDR(0xA02810)},
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.int_int_scan = {.phys = CALLIOPE_ADDR(0xA02818)},
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.ien_int_3 = {.phys = CALLIOPE_ADDR(0xA02830)},
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.ien_int_2 = {.phys = CALLIOPE_ADDR(0xA02834)},
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.ien_int_1 = {.phys = CALLIOPE_ADDR(0xA02838)},
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.ien_int_0 = {.phys = CALLIOPE_ADDR(0xA0283c)},
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.int_level_3_3 = {.phys = CALLIOPE_ADDR(0xA02880)},
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.int_level_3_2 = {.phys = CALLIOPE_ADDR(0xA02884)},
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.int_level_3_1 = {.phys = CALLIOPE_ADDR(0xA02888)},
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.int_level_3_0 = {.phys = CALLIOPE_ADDR(0xA0288c)},
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.int_level_2_3 = {.phys = CALLIOPE_ADDR(0xA02890)},
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.int_level_2_2 = {.phys = CALLIOPE_ADDR(0xA02894)},
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.int_level_2_1 = {.phys = CALLIOPE_ADDR(0xA02898)},
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.int_level_2_0 = {.phys = CALLIOPE_ADDR(0xA0289c)},
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.int_level_1_3 = {.phys = CALLIOPE_ADDR(0xA028a0)},
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.int_level_1_2 = {.phys = CALLIOPE_ADDR(0xA028a4)},
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.int_level_1_1 = {.phys = CALLIOPE_ADDR(0xA028a8)},
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.int_level_1_0 = {.phys = CALLIOPE_ADDR(0xA028ac)},
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.int_level_0_3 = {.phys = CALLIOPE_ADDR(0xA028b0)},
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.int_level_0_2 = {.phys = CALLIOPE_ADDR(0xA028b4)},
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.int_level_0_1 = {.phys = CALLIOPE_ADDR(0xA028b8)},
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.int_level_0_0 = {.phys = CALLIOPE_ADDR(0xA028bc)},
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.int_docsis_en = {.phys = CALLIOPE_ADDR(0xA028F4)},
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.mips_pll_setup = {.phys = CALLIOPE_ADDR(0x980000)},
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.fs432x4b4_usb_ctl = {.phys = CALLIOPE_ADDR(0x980030)},
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.test_bus = {.phys = CALLIOPE_ADDR(0x9800CC)},
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.crt_spare = {.phys = CALLIOPE_ADDR(0x9800d4)},
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.usb2_ohci_int_mask = {.phys = CALLIOPE_ADDR(0x9A000c)},
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.usb2_strap = {.phys = CALLIOPE_ADDR(0x9A0014)},
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.ehci_hcapbase = {.phys = CALLIOPE_ADDR(0x9BFE00)},
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.ohci_hc_revision = {.phys = CALLIOPE_ADDR(0x9BFC00)},
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.bcm1_bs_lmi_steer = {.phys = CALLIOPE_ADDR(0x9E0004)},
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.usb2_control = {.phys = CALLIOPE_ADDR(0x9E0054)},
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.usb2_stbus_obc = {.phys = CALLIOPE_ADDR(0x9BFF00)},
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.usb2_stbus_mess_size = {.phys = CALLIOPE_ADDR(0x9BFF04)},
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.usb2_stbus_chunk_size = {.phys = CALLIOPE_ADDR(0x9BFF08)},
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.pcie_regs = {.phys = 0x000000}, /* -doesn't exist- */
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.tim_ch = {.phys = CALLIOPE_ADDR(0xA02C10)},
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.tim_cl = {.phys = CALLIOPE_ADDR(0xA02C14)},
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.gpio_dout = {.phys = CALLIOPE_ADDR(0xA02c20)},
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.gpio_din = {.phys = CALLIOPE_ADDR(0xA02c24)},
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.gpio_dir = {.phys = CALLIOPE_ADDR(0xA02c2C)},
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.watchdog = {.phys = CALLIOPE_ADDR(0xA02c30)},
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.front_panel = {.phys = 0x000000}, /* -not used- */
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};
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