6b63f02318
add mmp specific clocks including apbc cloks, apmu clocks, and pll2, fraction clocks Signed-off-by: Chao Xie <xiechao.mail@gmail.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
97 lines
2.1 KiB
C
97 lines
2.1 KiB
C
/*
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* mmp AXI peripharal clock operation source file
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*
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* Copyright (C) 2012 Marvell
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* Chao Xie <xiechao.mail@gmail.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include "clk.h"
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#define to_clk_apmu(clk) (container_of(clk, struct clk_apmu, clk))
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struct clk_apmu {
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struct clk_hw hw;
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void __iomem *base;
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u32 rst_mask;
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u32 enable_mask;
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spinlock_t *lock;
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};
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static int clk_apmu_enable(struct clk_hw *hw)
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{
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struct clk_apmu *apmu = to_clk_apmu(hw);
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unsigned long data;
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unsigned long flags = 0;
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if (apmu->lock)
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spin_lock_irqsave(apmu->lock, flags);
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data = readl_relaxed(apmu->base) | apmu->enable_mask;
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writel_relaxed(data, apmu->base);
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if (apmu->lock)
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spin_unlock_irqrestore(apmu->lock, flags);
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return 0;
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}
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static void clk_apmu_disable(struct clk_hw *hw)
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{
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struct clk_apmu *apmu = to_clk_apmu(hw);
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unsigned long data;
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unsigned long flags = 0;
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if (apmu->lock)
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spin_lock_irqsave(apmu->lock, flags);
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data = readl_relaxed(apmu->base) & ~apmu->enable_mask;
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writel_relaxed(data, apmu->base);
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if (apmu->lock)
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spin_unlock_irqrestore(apmu->lock, flags);
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}
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struct clk_ops clk_apmu_ops = {
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.enable = clk_apmu_enable,
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.disable = clk_apmu_disable,
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};
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struct clk *mmp_clk_register_apmu(const char *name, const char *parent_name,
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void __iomem *base, u32 enable_mask, spinlock_t *lock)
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{
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struct clk_apmu *apmu;
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struct clk *clk;
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struct clk_init_data init;
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apmu = kzalloc(sizeof(*apmu), GFP_KERNEL);
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if (!apmu)
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return NULL;
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init.name = name;
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init.ops = &clk_apmu_ops;
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init.flags = CLK_SET_RATE_PARENT;
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init.parent_names = (parent_name ? &parent_name : NULL);
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init.num_parents = (parent_name ? 1 : 0);
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apmu->base = base;
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apmu->enable_mask = enable_mask;
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apmu->lock = lock;
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apmu->hw.init = &init;
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clk = clk_register(NULL, &apmu->hw);
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if (IS_ERR(clk))
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kfree(apmu);
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return clk;
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}
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