82f81f4784
We now throw all of the machvecs in to .machvec.init and either select one on the command line, or copy out the first (and usually only) one to sh_mv. The rest are freed as usual. This gets rid of all of the silly sh_mv aliasing and makes the selection explicit rather than link-order dependent. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
162 lines
3.7 KiB
C
162 lines
3.7 KiB
C
/*
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* linux/arch/sh/boards/se/770x/setup.c
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*
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* Copyright (C) 2000 Kazumoto Kojima
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*
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* Hitachi SolutionEngine Support.
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*
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*/
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <asm/machvec.h>
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#include <asm/se.h>
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#include <asm/io.h>
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#include <asm/smc37c93x.h>
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void init_se_IRQ(void);
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/*
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* Configure the Super I/O chip
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*/
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static void __init smsc_config(int index, int data)
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{
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outb_p(index, INDEX_PORT);
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outb_p(data, DATA_PORT);
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}
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/* XXX: Another candidate for a more generic cchip machine vector */
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static void __init smsc_setup(char **cmdline_p)
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{
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outb_p(CONFIG_ENTER, CONFIG_PORT);
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outb_p(CONFIG_ENTER, CONFIG_PORT);
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/* FDC */
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smsc_config(CURRENT_LDN_INDEX, LDN_FDC);
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smsc_config(ACTIVATE_INDEX, 0x01);
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smsc_config(IRQ_SELECT_INDEX, 6); /* IRQ6 */
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/* AUXIO (GPIO): to use IDE1 */
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smsc_config(CURRENT_LDN_INDEX, LDN_AUXIO);
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smsc_config(GPIO46_INDEX, 0x00); /* nIOROP */
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smsc_config(GPIO47_INDEX, 0x00); /* nIOWOP */
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/* COM1 */
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smsc_config(CURRENT_LDN_INDEX, LDN_COM1);
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smsc_config(ACTIVATE_INDEX, 0x01);
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smsc_config(IO_BASE_HI_INDEX, 0x03);
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smsc_config(IO_BASE_LO_INDEX, 0xf8);
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smsc_config(IRQ_SELECT_INDEX, 4); /* IRQ4 */
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/* COM2 */
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smsc_config(CURRENT_LDN_INDEX, LDN_COM2);
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smsc_config(ACTIVATE_INDEX, 0x01);
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smsc_config(IO_BASE_HI_INDEX, 0x02);
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smsc_config(IO_BASE_LO_INDEX, 0xf8);
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smsc_config(IRQ_SELECT_INDEX, 3); /* IRQ3 */
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/* RTC */
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smsc_config(CURRENT_LDN_INDEX, LDN_RTC);
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smsc_config(ACTIVATE_INDEX, 0x01);
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smsc_config(IRQ_SELECT_INDEX, 8); /* IRQ8 */
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/* XXX: PARPORT, KBD, and MOUSE will come here... */
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outb_p(CONFIG_EXIT, CONFIG_PORT);
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}
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static struct resource cf_ide_resources[] = {
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[0] = {
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.start = PA_MRSHPC_IO + 0x1f0,
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.end = PA_MRSHPC_IO + 0x1f0 + 8,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = PA_MRSHPC_IO + 0x1f0 + 0x206,
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.end = PA_MRSHPC_IO + 0x1f0 +8 + 0x206 + 8,
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.flags = IORESOURCE_MEM,
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},
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[2] = {
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.start = IRQ_CFCARD,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device cf_ide_device = {
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.name = "pata_platform",
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.id = -1,
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.num_resources = ARRAY_SIZE(cf_ide_resources),
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.resource = cf_ide_resources,
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};
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static unsigned char heartbeat_bit_pos[] = { 8, 9, 10, 11, 12, 13, 14, 15 };
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static struct resource heartbeat_resources[] = {
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[0] = {
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.start = PA_LED,
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.end = PA_LED + ARRAY_SIZE(heartbeat_bit_pos) - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device heartbeat_device = {
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.name = "heartbeat",
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.id = -1,
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.dev = {
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.platform_data = heartbeat_bit_pos,
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},
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.num_resources = ARRAY_SIZE(heartbeat_resources),
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.resource = heartbeat_resources,
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};
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static struct platform_device *se_devices[] __initdata = {
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&heartbeat_device,
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&cf_ide_device,
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};
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static int __init se_devices_setup(void)
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{
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return platform_add_devices(se_devices, ARRAY_SIZE(se_devices));
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}
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device_initcall(se_devices_setup);
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/*
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* The Machine Vector
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*/
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static struct sh_machine_vector mv_se __initmv = {
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.mv_name = "SolutionEngine",
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.mv_setup = smsc_setup,
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#if defined(CONFIG_CPU_SH4)
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.mv_nr_irqs = 48,
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#elif defined(CONFIG_CPU_SUBTYPE_SH7708)
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.mv_nr_irqs = 32,
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#elif defined(CONFIG_CPU_SUBTYPE_SH7709)
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.mv_nr_irqs = 61,
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#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
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.mv_nr_irqs = 86,
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#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
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.mv_nr_irqs = 104,
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#endif
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.mv_inb = se_inb,
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.mv_inw = se_inw,
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.mv_inl = se_inl,
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.mv_outb = se_outb,
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.mv_outw = se_outw,
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.mv_outl = se_outl,
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.mv_inb_p = se_inb_p,
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.mv_inw_p = se_inw,
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.mv_inl_p = se_inl,
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.mv_outb_p = se_outb_p,
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.mv_outw_p = se_outw,
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.mv_outl_p = se_outl,
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.mv_insb = se_insb,
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.mv_insw = se_insw,
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.mv_insl = se_insl,
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.mv_outsb = se_outsb,
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.mv_outsw = se_outsw,
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.mv_outsl = se_outsl,
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.mv_init_irq = init_se_IRQ,
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};
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