2a4aca1144
Currently, the various forms of low level TLB invalidations are all implemented in misc_32.S for 32-bit processors, in a fairly scary mess of #ifdef's and with interesting duplication such as a whole bunch of code for FSL _tlbie and _tlbia which are no longer used. This moves things around such that _tlbie is now defined in hash_low_32.S and is only used by the 32-bit hash code, and all nohash CPUs use the various _tlbil_* forms that are now moved to a new file, tlb_nohash_low.S. I moved all the definitions for that stuff out of include/asm/tlbflush.h as they are really internal mm stuff, into mm/mmu_decl.h The code should have no functional changes. I kept some variants inline for trivial forms on things like 40x and 8xx. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
168 lines
4.6 KiB
C
168 lines
4.6 KiB
C
#ifndef _ASM_POWERPC_TLBFLUSH_H
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#define _ASM_POWERPC_TLBFLUSH_H
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/*
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* TLB flushing:
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*
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* - flush_tlb_mm(mm) flushes the specified mm context TLB's
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* - flush_tlb_page(vma, vmaddr) flushes one page
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* - local_flush_tlb_mm(mm) flushes the specified mm context on
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* the local processor
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* - local_flush_tlb_page(vma, vmaddr) flushes one page on the local processor
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* - flush_tlb_page_nohash(vma, vmaddr) flushes one page if SW loaded TLB
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* - flush_tlb_range(vma, start, end) flushes a range of pages
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* - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifdef __KERNEL__
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#ifdef CONFIG_PPC_MMU_NOHASH
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/*
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* TLB flushing for software loaded TLB chips
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*
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* TODO: (CONFIG_FSL_BOOKE) determine if flush_tlb_range &
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* flush_tlb_kernel_range are best implemented as tlbia vs
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* specific tlbie's
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*/
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#include <linux/mm.h>
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#define MMU_NO_CONTEXT ((unsigned int)-1)
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extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end);
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extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
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extern void local_flush_tlb_mm(struct mm_struct *mm);
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extern void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
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#ifdef CONFIG_SMP
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extern void flush_tlb_mm(struct mm_struct *mm);
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extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
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#else
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#define flush_tlb_mm(mm) local_flush_tlb_mm(mm)
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#define flush_tlb_page(vma,addr) local_flush_tlb_page(vma,addr)
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#endif
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#define flush_tlb_page_nohash(vma,addr) flush_tlb_page(vma,addr)
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#elif defined(CONFIG_PPC_STD_MMU_32)
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/*
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* TLB flushing for "classic" hash-MMU 32-bit CPUs, 6xx, 7xx, 7xxx
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*/
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extern void flush_tlb_mm(struct mm_struct *mm);
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extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
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extern void flush_tlb_page_nohash(struct vm_area_struct *vma, unsigned long addr);
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extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end);
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extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
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static inline void local_flush_tlb_page(struct vm_area_struct *vma,
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unsigned long vmaddr)
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{
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flush_tlb_page(vma, vmaddr);
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}
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static inline void local_flush_tlb_mm(struct mm_struct *mm)
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{
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flush_tlb_mm(mm);
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}
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#elif defined(CONFIG_PPC_STD_MMU_64)
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/*
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* TLB flushing for 64-bit hash-MMU CPUs
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*/
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#include <linux/percpu.h>
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#include <asm/page.h>
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#define PPC64_TLB_BATCH_NR 192
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struct ppc64_tlb_batch {
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int active;
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unsigned long index;
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struct mm_struct *mm;
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real_pte_t pte[PPC64_TLB_BATCH_NR];
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unsigned long vaddr[PPC64_TLB_BATCH_NR];
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unsigned int psize;
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int ssize;
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};
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DECLARE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);
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extern void __flush_tlb_pending(struct ppc64_tlb_batch *batch);
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extern void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep, unsigned long pte, int huge);
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#define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
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static inline void arch_enter_lazy_mmu_mode(void)
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{
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struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
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batch->active = 1;
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}
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static inline void arch_leave_lazy_mmu_mode(void)
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{
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struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
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if (batch->index)
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__flush_tlb_pending(batch);
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batch->active = 0;
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}
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#define arch_flush_lazy_mmu_mode() do {} while (0)
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extern void flush_hash_page(unsigned long va, real_pte_t pte, int psize,
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int ssize, int local);
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extern void flush_hash_range(unsigned long number, int local);
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static inline void local_flush_tlb_mm(struct mm_struct *mm)
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{
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}
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static inline void flush_tlb_mm(struct mm_struct *mm)
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{
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}
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static inline void local_flush_tlb_page(struct vm_area_struct *vma,
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unsigned long vmaddr)
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{
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}
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static inline void flush_tlb_page(struct vm_area_struct *vma,
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unsigned long vmaddr)
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{
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}
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static inline void flush_tlb_page_nohash(struct vm_area_struct *vma,
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unsigned long vmaddr)
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{
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}
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static inline void flush_tlb_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end)
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{
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}
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static inline void flush_tlb_kernel_range(unsigned long start,
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unsigned long end)
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{
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}
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/* Private function for use by PCI IO mapping code */
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extern void __flush_hash_table_range(struct mm_struct *mm, unsigned long start,
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unsigned long end);
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#else
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#error Unsupported MMU type
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#endif
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#endif /*__KERNEL__ */
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#endif /* _ASM_POWERPC_TLBFLUSH_H */
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