A PCIe downstream port is a P2P bridge.  Its secondary interface is
a link that should lead only to device 0 (unless ARI is enabled)[1], so
we don't probe for non-zero device numbers.
Some Stratus ftServer systems have a PCIe downstream port (02:00.0) that
leads to both an upstream port (03:00.0) and a downstream port (03:01.0),
and 03:01.0 has important devices below it:
  [0000:02]-+-00.0-[03-3c]--+-00.0-[04-09]--...
                            \-01.0-[0a-0d]--+-[USB]
                                            +-[NIC]
                                            +-...
Previously, we didn't enumerate device 03:01.0, so USB and the network
didn't work.  This patch adds a DMI quirk to scan all device numbers,
not just 0, below a downstream port.
Based on a patch by Prarit Bhargava.
[1] PCIe spec r3.0, sec 7.3.1
CC: Myron Stowe <mstowe@redhat.com>
CC: Don Dutile <ddutile@redhat.com>
CC: James Paradis <james.paradis@stratus.com>
CC: Matthew Wilcox <matthew.r.wilcox@intel.com>
CC: Jesse Barnes <jbarnes@virtuousgeek.org>
CC: Prarit Bhargava <prarit@redhat.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
		
	
			
		
			
				
	
	
		
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			74 lines
		
	
	
	
		
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/*
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 * This program is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU General Public License
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 * as published by the Free Software Foundation; either version
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 * 2 of the License, or (at your option) any later version.
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 */
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#ifndef _ASM_GENERIC_PCI_BRIDGE_H
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#define _ASM_GENERIC_PCI_BRIDGE_H
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#ifdef __KERNEL__
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enum {
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	/* Force re-assigning all resources (ignore firmware
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	 * setup completely)
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	 */
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	PCI_REASSIGN_ALL_RSRC	= 0x00000001,
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	/* Re-assign all bus numbers */
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	PCI_REASSIGN_ALL_BUS	= 0x00000002,
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	/* Do not try to assign, just use existing setup */
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	PCI_PROBE_ONLY		= 0x00000004,
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	/* Don't bother with ISA alignment unless the bridge has
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	 * ISA forwarding enabled
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	 */
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	PCI_CAN_SKIP_ISA_ALIGN	= 0x00000008,
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	/* Enable domain numbers in /proc */
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	PCI_ENABLE_PROC_DOMAINS	= 0x00000010,
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	/* ... except for domain 0 */
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	PCI_COMPAT_DOMAIN_0	= 0x00000020,
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	/* PCIe downstream ports are bridges that normally lead to only a
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	 * device 0, but if this is set, we scan all possible devices, not
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	 * just device 0.
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	 */
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	PCI_SCAN_ALL_PCIE_DEVS	= 0x00000040,
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};
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#ifdef CONFIG_PCI
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extern unsigned int pci_flags;
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static inline void pci_set_flags(int flags)
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{
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	pci_flags = flags;
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}
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static inline void pci_add_flags(int flags)
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{
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	pci_flags |= flags;
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}
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static inline void pci_clear_flags(int flags)
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{
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	pci_flags &= ~flags;
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}
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static inline int pci_has_flag(int flag)
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{
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	return pci_flags & flag;
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}
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#else
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static inline void pci_set_flags(int flags) { }
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static inline void pci_add_flags(int flags) { }
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static inline void pci_clear_flags(int flags) { }
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static inline int pci_has_flag(int flag)
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{
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	return 0;
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}
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#endif	/* CONFIG_PCI */
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#endif	/* __KERNEL__ */
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#endif	/* _ASM_GENERIC_PCI_BRIDGE_H */
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