 9ed96e87c5
			
		
	
	
	9ed96e87c5
	
	
	
		
			
			Limit PIT timer frequency similarly to the limit applied by LAPIC timer. Cc: stable@kernel.org Reviewed-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
		
			
				
	
	
		
			131 lines
		
	
	
	
		
			3.1 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			131 lines
		
	
	
	
		
			3.1 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
| #ifndef ARCH_X86_KVM_X86_H
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| #define ARCH_X86_KVM_X86_H
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| 
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| #include <linux/kvm_host.h>
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| #include "kvm_cache_regs.h"
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| 
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| static inline void kvm_clear_exception_queue(struct kvm_vcpu *vcpu)
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| {
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| 	vcpu->arch.exception.pending = false;
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| }
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| 
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| static inline void kvm_queue_interrupt(struct kvm_vcpu *vcpu, u8 vector,
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| 	bool soft)
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| {
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| 	vcpu->arch.interrupt.pending = true;
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| 	vcpu->arch.interrupt.soft = soft;
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| 	vcpu->arch.interrupt.nr = vector;
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| }
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| 
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| static inline void kvm_clear_interrupt_queue(struct kvm_vcpu *vcpu)
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| {
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| 	vcpu->arch.interrupt.pending = false;
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| }
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| 
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| static inline bool kvm_event_needs_reinjection(struct kvm_vcpu *vcpu)
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| {
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| 	return vcpu->arch.exception.pending || vcpu->arch.interrupt.pending ||
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| 		vcpu->arch.nmi_injected;
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| }
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| 
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| static inline bool kvm_exception_is_soft(unsigned int nr)
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| {
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| 	return (nr == BP_VECTOR) || (nr == OF_VECTOR);
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| }
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| 
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| static inline bool is_protmode(struct kvm_vcpu *vcpu)
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| {
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| 	return kvm_read_cr0_bits(vcpu, X86_CR0_PE);
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| }
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| 
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| static inline int is_long_mode(struct kvm_vcpu *vcpu)
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| {
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| #ifdef CONFIG_X86_64
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| 	return vcpu->arch.efer & EFER_LMA;
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| #else
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| 	return 0;
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| #endif
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| }
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| 
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| static inline bool mmu_is_nested(struct kvm_vcpu *vcpu)
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| {
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| 	return vcpu->arch.walk_mmu == &vcpu->arch.nested_mmu;
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| }
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| 
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| static inline int is_pae(struct kvm_vcpu *vcpu)
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| {
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| 	return kvm_read_cr4_bits(vcpu, X86_CR4_PAE);
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| }
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| 
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| static inline int is_pse(struct kvm_vcpu *vcpu)
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| {
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| 	return kvm_read_cr4_bits(vcpu, X86_CR4_PSE);
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| }
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| 
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| static inline int is_paging(struct kvm_vcpu *vcpu)
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| {
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| 	return likely(kvm_read_cr0_bits(vcpu, X86_CR0_PG));
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| }
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| 
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| static inline u32 bit(int bitno)
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| {
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| 	return 1 << (bitno & 31);
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| }
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| 
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| static inline void vcpu_cache_mmio_info(struct kvm_vcpu *vcpu,
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| 					gva_t gva, gfn_t gfn, unsigned access)
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| {
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| 	vcpu->arch.mmio_gva = gva & PAGE_MASK;
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| 	vcpu->arch.access = access;
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| 	vcpu->arch.mmio_gfn = gfn;
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| }
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| 
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| /*
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|  * Clear the mmio cache info for the given gva,
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|  * specially, if gva is ~0ul, we clear all mmio cache info.
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|  */
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| static inline void vcpu_clear_mmio_info(struct kvm_vcpu *vcpu, gva_t gva)
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| {
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| 	if (gva != (~0ul) && vcpu->arch.mmio_gva != (gva & PAGE_MASK))
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| 		return;
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| 
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| 	vcpu->arch.mmio_gva = 0;
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| }
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| 
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| static inline bool vcpu_match_mmio_gva(struct kvm_vcpu *vcpu, unsigned long gva)
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| {
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| 	if (vcpu->arch.mmio_gva && vcpu->arch.mmio_gva == (gva & PAGE_MASK))
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| 		return true;
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| 
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| 	return false;
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| }
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| 
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| static inline bool vcpu_match_mmio_gpa(struct kvm_vcpu *vcpu, gpa_t gpa)
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| {
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| 	if (vcpu->arch.mmio_gfn && vcpu->arch.mmio_gfn == gpa >> PAGE_SHIFT)
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| 		return true;
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| 
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| 	return false;
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| }
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| 
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| void kvm_before_handle_nmi(struct kvm_vcpu *vcpu);
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| void kvm_after_handle_nmi(struct kvm_vcpu *vcpu);
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| int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip);
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| 
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| void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr);
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| 
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| int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
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| 	gva_t addr, void *val, unsigned int bytes,
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| 	struct x86_exception *exception);
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| 
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| int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
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| 	gva_t addr, void *val, unsigned int bytes,
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| 	struct x86_exception *exception);
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| 
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| #define KVM_SUPPORTED_XCR0	(XSTATE_FP | XSTATE_SSE | XSTATE_YMM)
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| extern u64 host_xcr0;
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| 
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| extern unsigned int min_timer_period_us;
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| 
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| extern struct static_key kvm_no_apic_vcpu;
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| #endif
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