Yonghong Song ed8dfc46e0 MIPS: Netlogic: L1D cacheflush before thread enable on XLPII ... On XLPII CPUs, the L1D cache has to be flushed with regular cache operations before enabling threads in a core. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6276/		2014-01-24 22:39:47 +01:00
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common	MIPS: Netlogic: L1D cacheflush before thread enable on XLPII	2014-01-24 22:39:47 +01:00
dts	MIPS: Netlogic: Built-in DTB for XLP2xx SoC boards	2013-09-03 23:22:20 +02:00
xlp	MIPS: Netlogic: Add MSI support for XLP	2014-01-24 22:39:46 +01:00
xlr	MIPS: Cleanup CP0 PRId and CP1 FPIR register access masks	2013-09-18 20:25:19 +02:00
Kconfig	MIPS: Netlogic: Built-in DTB for XLP2xx SoC boards	2013-09-03 23:22:20 +02:00
Makefile	MIPS: Netlogic: Add support for built in DTB	2012-08-22 23:46:37 +02:00
Platform	MIPS: Whitespace cleanup.	2013-02-01 10:00:22 +01:00