 d5e9fe8462
			
		
	
	
	d5e9fe8462
	
	
	
		
			
			Add minimal device tree data for Keystone2 based SOCs. Patch contains mainly ARM related SOC data and nothing about EVM specific yet. Cc: Grant Likely <grant.likely@linaro.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: arm@kernel.org Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
		
			
				
	
	
		
			117 lines
		
	
	
	
		
			2.2 KiB
			
		
	
	
	
		
			Text
		
	
	
	
	
	
			
		
		
	
	
			117 lines
		
	
	
	
		
			2.2 KiB
			
		
	
	
	
		
			Text
		
	
	
	
	
	
| /*
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|  * Copyright 2013 Texas Instruments, Inc.
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|  *
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|  * This program is free software; you can redistribute it and/or modify
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|  * it under the terms of the GNU General Public License version 2 as
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|  * published by the Free Software Foundation.
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|  */
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| 
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| /dts-v1/;
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| /include/ "skeleton.dtsi"
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| 
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| / {
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| 	model = "Texas Instruments Keystone 2 SoC";
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| 	compatible =  "ti,keystone-evm";
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| 	#address-cells = <2>;
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| 	#size-cells = <2>;
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| 	interrupt-parent = <&gic>;
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| 
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| 	aliases {
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| 		serial0	= &uart0;
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| 	};
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| 
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| 	memory {
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| 		reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
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| 	};
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| 
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| 	cpus {
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| 		#address-cells = <1>;
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| 		#size-cells = <0>;
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| 
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| 		interrupt-parent = <&gic>;
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| 
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| 		cpu@0 {
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| 			compatible = "arm,cortex-a15";
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| 			device_type = "cpu";
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| 			reg = <0>;
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| 		};
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| 
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| 		cpu@1 {
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| 			compatible = "arm,cortex-a15";
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| 			device_type = "cpu";
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| 			reg = <1>;
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| 		};
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| 
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| 		cpu@2 {
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| 			compatible = "arm,cortex-a15";
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| 			device_type = "cpu";
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| 			reg = <2>;
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| 		};
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| 
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| 		cpu@3 {
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| 			compatible = "arm,cortex-a15";
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| 			device_type = "cpu";
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| 			reg = <3>;
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| 		};
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| 	};
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| 
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| 	gic: interrupt-controller {
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| 		compatible = "arm,cortex-a15-gic";
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| 		#interrupt-cells = <3>;
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| 		#size-cells = <0>;
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| 		#address-cells = <1>;
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| 		interrupt-controller;
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| 		reg = <0x0 0x02561000 0x0 0x1000>,
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| 		      <0x0 0x02562000 0x0 0x2000>;
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| 	};
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| 
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| 	timer {
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| 		compatible = "arm,armv7-timer";
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| 		interrupts = <1 13 0xf08>,
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| 			     <1 14 0xf08>,
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| 			     <1 11 0xf08>,
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| 			     <1 10 0x308>;
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| 	};
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| 
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| 	pmu {
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| 		compatible = "arm,cortex-a15-pmu";
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| 		interrupts = <0 20 0xf01>,
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| 			     <0 21 0xf01>,
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| 			     <0 22 0xf01>,
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| 			     <0 23 0xf01>;
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| 	};
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| 
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| 	soc {
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| 		#address-cells = <1>;
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| 		#size-cells = <1>;
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| 		compatible = "ti,keystone","simple-bus";
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| 		interrupt-parent = <&gic>;
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| 		ranges = <0x0 0x0 0x0 0xc0000000>;
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| 
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| 		rstctrl: reset-controller {
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| 			compatible = "ti,keystone-reset";
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| 			reg = <0x023100e8 4>;	/* pll reset control reg */
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| 		};
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| 
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| 		uart0: serial@02530c00 {
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| 			compatible = "ns16550a";
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| 			current-speed = <115200>;
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| 			reg-shift = <2>;
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| 			reg-io-width = <4>;
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| 			reg = <0x02530c00 0x100>;
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| 			clock-frequency = <133120000>;
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| 			interrupts = <0 277 0xf01>;
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| 		};
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| 
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| 		uart1:	serial@02531000 {
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| 			compatible = "ns16550a";
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| 			current-speed = <115200>;
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| 			reg-shift = <2>;
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| 			reg-io-width = <4>;
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| 			reg = <0x02531000 0x100>;
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| 			clock-frequency = <133120000>;
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| 			interrupts = <0 280 0xf01>;
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| 		};
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| 
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| 	};
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| };
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