ea75159ee6
On OMAP3, the pixel clock for the LCD manager was derived through DISPC_FCLK as: Lcd Pixel clock = DISPC_FCLK / lcd / pcd Where lcd and pcd are divisors in the DISPC_DIVISOR register. On OMAP4, the pixel clocks for LCD1 and LCD2 managers are derived from 2 new clocks named LCD1_CLK and LCD2_CLK. The pixel clocks are calculated as: Lcd_o Pixel clock = LCDo_CLK / lcdo /pcdo, o = 1, 2 Where lcdo and pcdo registers are divisors in DISPC_DIVISORo registers. LCD1_CLK and LCD2_CLK can have DSS_FCLK, and the M4 divider clocks of DSI1 PLL and DSI2 PLL as clock sources respectively. Introduce functions to select and get the clock source for these new clocks. Modify DISPC functions get the correct lck and pck rates based on the clock source of these clocks. Since OMAP2/3 don't have these clocks, force OMAP2/3 to always have the LCD_CLK source as DSS_CLK_SRC_FCK by introducing a dss feature. Introduce clock source names for OMAP4 and some register field changes in DSS_CTRL on OMAP4. Currently, LCD2_CLK can only have DSS_FCLK as its clock source as DSI2 PLL functionality hasn't been introduced yet. BUG for now if DSI2 PLL is selected as clock. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
321 lines
9.3 KiB
C
321 lines
9.3 KiB
C
/*
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* linux/drivers/video/omap2/dss/dss_features.c
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*
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* Copyright (C) 2010 Texas Instruments
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* Author: Archit Taneja <archit@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/err.h>
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#include <linux/slab.h>
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#include <plat/display.h>
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#include <plat/cpu.h>
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#include "dss.h"
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#include "dss_features.h"
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/* Defines a generic omap register field */
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struct dss_reg_field {
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enum dss_feat_reg_field id;
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u8 start, end;
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};
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struct omap_dss_features {
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const struct dss_reg_field *reg_fields;
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const int num_reg_fields;
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const u32 has_feature;
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const int num_mgrs;
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const int num_ovls;
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const unsigned long max_dss_fck;
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const enum omap_display_type *supported_displays;
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const enum omap_color_mode *supported_color_modes;
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const struct dss_clk_source_name *clksrc_names;
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};
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/* This struct is assigned to one of the below during initialization */
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static struct omap_dss_features *omap_current_dss_features;
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static const struct dss_reg_field omap2_dss_reg_fields[] = {
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{ FEAT_REG_FIRHINC, 11, 0 },
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{ FEAT_REG_FIRVINC, 27, 16 },
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{ FEAT_REG_FIFOLOWTHRESHOLD, 8, 0 },
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{ FEAT_REG_FIFOHIGHTHRESHOLD, 24, 16 },
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{ FEAT_REG_FIFOSIZE, 8, 0 },
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{ FEAT_REG_HORIZONTALACCU, 9, 0 },
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{ FEAT_REG_VERTICALACCU, 25, 16 },
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{ FEAT_REG_DISPC_CLK_SWITCH, 0, 0 },
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};
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static const struct dss_reg_field omap3_dss_reg_fields[] = {
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{ FEAT_REG_FIRHINC, 12, 0 },
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{ FEAT_REG_FIRVINC, 28, 16 },
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{ FEAT_REG_FIFOLOWTHRESHOLD, 11, 0 },
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{ FEAT_REG_FIFOHIGHTHRESHOLD, 27, 16 },
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{ FEAT_REG_FIFOSIZE, 10, 0 },
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{ FEAT_REG_HORIZONTALACCU, 9, 0 },
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{ FEAT_REG_VERTICALACCU, 25, 16 },
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{ FEAT_REG_DISPC_CLK_SWITCH, 0, 0 },
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};
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static const struct dss_reg_field omap4_dss_reg_fields[] = {
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{ FEAT_REG_FIRHINC, 12, 0 },
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{ FEAT_REG_FIRVINC, 28, 16 },
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{ FEAT_REG_FIFOLOWTHRESHOLD, 15, 0 },
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{ FEAT_REG_FIFOHIGHTHRESHOLD, 31, 16 },
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{ FEAT_REG_FIFOSIZE, 15, 0 },
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{ FEAT_REG_HORIZONTALACCU, 10, 0 },
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{ FEAT_REG_VERTICALACCU, 26, 16 },
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{ FEAT_REG_DISPC_CLK_SWITCH, 9, 8 },
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};
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static const enum omap_display_type omap2_dss_supported_displays[] = {
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/* OMAP_DSS_CHANNEL_LCD */
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OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI,
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/* OMAP_DSS_CHANNEL_DIGIT */
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OMAP_DISPLAY_TYPE_VENC,
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};
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static const enum omap_display_type omap3430_dss_supported_displays[] = {
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/* OMAP_DSS_CHANNEL_LCD */
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OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
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OMAP_DISPLAY_TYPE_SDI | OMAP_DISPLAY_TYPE_DSI,
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/* OMAP_DSS_CHANNEL_DIGIT */
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OMAP_DISPLAY_TYPE_VENC,
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};
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static const enum omap_display_type omap3630_dss_supported_displays[] = {
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/* OMAP_DSS_CHANNEL_LCD */
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OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
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OMAP_DISPLAY_TYPE_DSI,
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/* OMAP_DSS_CHANNEL_DIGIT */
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OMAP_DISPLAY_TYPE_VENC,
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};
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static const enum omap_display_type omap4_dss_supported_displays[] = {
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/* OMAP_DSS_CHANNEL_LCD */
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OMAP_DISPLAY_TYPE_DBI | OMAP_DISPLAY_TYPE_DSI,
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/* OMAP_DSS_CHANNEL_DIGIT */
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OMAP_DISPLAY_TYPE_VENC,
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/* OMAP_DSS_CHANNEL_LCD2 */
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OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
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OMAP_DISPLAY_TYPE_DSI,
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};
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static const enum omap_color_mode omap2_dss_supported_color_modes[] = {
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/* OMAP_DSS_GFX */
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OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
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OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
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OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
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OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P,
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/* OMAP_DSS_VIDEO1 */
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OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
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OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
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OMAP_DSS_COLOR_UYVY,
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/* OMAP_DSS_VIDEO2 */
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OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
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OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
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OMAP_DSS_COLOR_UYVY,
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};
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static const enum omap_color_mode omap3_dss_supported_color_modes[] = {
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/* OMAP_DSS_GFX */
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OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
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OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
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OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
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OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
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OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
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OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
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/* OMAP_DSS_VIDEO1 */
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OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P |
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OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
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OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY,
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/* OMAP_DSS_VIDEO2 */
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OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
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OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
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OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
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OMAP_DSS_COLOR_UYVY | OMAP_DSS_COLOR_ARGB32 |
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OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
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};
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static const struct dss_clk_source_name omap2_dss_clk_source_names[] = {
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{ DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, "N/A" },
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{ DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, "N/A" },
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{ DSS_CLK_SRC_FCK, "DSS_FCLK1" },
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};
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static const struct dss_clk_source_name omap3_dss_clk_source_names[] = {
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{ DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, "DSI1_PLL_FCLK" },
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{ DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, "DSI2_PLL_FCLK" },
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{ DSS_CLK_SRC_FCK, "DSS1_ALWON_FCLK" },
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};
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static const struct dss_clk_source_name omap4_dss_clk_source_names[] = {
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{ DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, "PLL1_CLK1" },
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{ DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, "PLL1_CLK2" },
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{ DSS_CLK_SRC_FCK, "DSS_FCLK" },
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};
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/* OMAP2 DSS Features */
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static struct omap_dss_features omap2_dss_features = {
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.reg_fields = omap2_dss_reg_fields,
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.num_reg_fields = ARRAY_SIZE(omap2_dss_reg_fields),
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.has_feature =
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FEAT_LCDENABLEPOL | FEAT_LCDENABLESIGNAL |
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FEAT_PCKFREEENABLE | FEAT_FUNCGATED |
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FEAT_ROWREPEATENABLE | FEAT_RESIZECONF,
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.num_mgrs = 2,
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.num_ovls = 3,
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.max_dss_fck = 173000000,
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.supported_displays = omap2_dss_supported_displays,
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.supported_color_modes = omap2_dss_supported_color_modes,
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.clksrc_names = omap2_dss_clk_source_names,
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};
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/* OMAP3 DSS Features */
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static struct omap_dss_features omap3430_dss_features = {
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.reg_fields = omap3_dss_reg_fields,
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.num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
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.has_feature =
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FEAT_GLOBAL_ALPHA | FEAT_LCDENABLEPOL |
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FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE |
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FEAT_FUNCGATED | FEAT_ROWREPEATENABLE |
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FEAT_LINEBUFFERSPLIT | FEAT_RESIZECONF,
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.num_mgrs = 2,
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.num_ovls = 3,
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.max_dss_fck = 173000000,
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.supported_displays = omap3430_dss_supported_displays,
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.supported_color_modes = omap3_dss_supported_color_modes,
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.clksrc_names = omap3_dss_clk_source_names,
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};
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static struct omap_dss_features omap3630_dss_features = {
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.reg_fields = omap3_dss_reg_fields,
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.num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
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.has_feature =
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FEAT_GLOBAL_ALPHA | FEAT_LCDENABLEPOL |
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FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE |
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FEAT_PRE_MULT_ALPHA | FEAT_FUNCGATED |
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FEAT_ROWREPEATENABLE | FEAT_LINEBUFFERSPLIT |
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FEAT_RESIZECONF,
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.num_mgrs = 2,
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.num_ovls = 3,
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.max_dss_fck = 173000000,
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.supported_displays = omap3630_dss_supported_displays,
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.supported_color_modes = omap3_dss_supported_color_modes,
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.clksrc_names = omap3_dss_clk_source_names,
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};
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/* OMAP4 DSS Features */
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static struct omap_dss_features omap4_dss_features = {
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.reg_fields = omap4_dss_reg_fields,
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.num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
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.has_feature =
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FEAT_GLOBAL_ALPHA | FEAT_PRE_MULT_ALPHA |
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FEAT_MGR_LCD2 | FEAT_GLOBAL_ALPHA_VID1 |
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FEAT_CORE_CLK_DIV | FEAT_LCD_CLK_SRC,
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.num_mgrs = 3,
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.num_ovls = 3,
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.max_dss_fck = 186000000,
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.supported_displays = omap4_dss_supported_displays,
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.supported_color_modes = omap3_dss_supported_color_modes,
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.clksrc_names = omap4_dss_clk_source_names,
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};
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/* Functions returning values related to a DSS feature */
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int dss_feat_get_num_mgrs(void)
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{
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return omap_current_dss_features->num_mgrs;
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}
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int dss_feat_get_num_ovls(void)
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{
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return omap_current_dss_features->num_ovls;
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}
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/* Max supported DSS FCK in Hz */
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unsigned long dss_feat_get_max_dss_fck(void)
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{
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return omap_current_dss_features->max_dss_fck;
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}
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enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel)
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{
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return omap_current_dss_features->supported_displays[channel];
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}
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enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane)
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{
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return omap_current_dss_features->supported_color_modes[plane];
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}
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bool dss_feat_color_mode_supported(enum omap_plane plane,
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enum omap_color_mode color_mode)
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{
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return omap_current_dss_features->supported_color_modes[plane] &
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color_mode;
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}
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const char *dss_feat_get_clk_source_name(enum dss_clk_source id)
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{
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return omap_current_dss_features->clksrc_names[id].clksrc_name;
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}
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/* DSS has_feature check */
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bool dss_has_feature(enum dss_feat_id id)
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{
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return omap_current_dss_features->has_feature & id;
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}
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void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end)
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{
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if (id >= omap_current_dss_features->num_reg_fields)
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BUG();
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*start = omap_current_dss_features->reg_fields[id].start;
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*end = omap_current_dss_features->reg_fields[id].end;
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}
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void dss_features_init(void)
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{
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if (cpu_is_omap24xx())
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omap_current_dss_features = &omap2_dss_features;
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else if (cpu_is_omap3630())
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omap_current_dss_features = &omap3630_dss_features;
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else if (cpu_is_omap34xx())
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omap_current_dss_features = &omap3430_dss_features;
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else
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omap_current_dss_features = &omap4_dss_features;
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}
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