14e968bad7
This covers the UP / SMP (with no hardware assist for atomic r-m-w) as well as ARC700 LLOCK/SCOND insns based. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
143 lines
3.8 KiB
C
143 lines
3.8 KiB
C
/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARC_CMPXCHG_H
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#define __ASM_ARC_CMPXCHG_H
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#include <linux/types.h>
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#include <asm/smp.h>
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#ifdef CONFIG_ARC_HAS_LLSC
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static inline unsigned long
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__cmpxchg(volatile void *ptr, unsigned long expected, unsigned long new)
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{
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unsigned long prev;
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__asm__ __volatile__(
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"1: llock %0, [%1] \n"
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" brne %0, %2, 2f \n"
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" scond %3, [%1] \n"
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" bnz 1b \n"
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"2: \n"
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: "=&r"(prev)
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: "r"(ptr), "ir"(expected),
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"r"(new) /* can't be "ir". scond can't take limm for "b" */
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: "cc");
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return prev;
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}
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#else
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static inline unsigned long
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__cmpxchg(volatile void *ptr, unsigned long expected, unsigned long new)
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{
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unsigned long flags;
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int prev;
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volatile unsigned long *p = ptr;
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atomic_ops_lock(flags);
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prev = *p;
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if (prev == expected)
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*p = new;
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atomic_ops_unlock(flags);
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return prev;
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}
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#endif /* CONFIG_ARC_HAS_LLSC */
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#define cmpxchg(ptr, o, n) ((typeof(*(ptr)))__cmpxchg((ptr), \
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(unsigned long)(o), (unsigned long)(n)))
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/*
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* Since not supported natively, ARC cmpxchg() uses atomic_ops_lock (UP/SMP)
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* just to gaurantee semantics.
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* atomic_cmpxchg() needs to use the same locks as it's other atomic siblings
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* which also happens to be atomic_ops_lock.
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*
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* Thus despite semantically being different, implementation of atomic_cmpxchg()
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* is same as cmpxchg().
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*/
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#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
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/*
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* xchg (reg with memory) based on "Native atomic" EX insn
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*/
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static inline unsigned long __xchg(unsigned long val, volatile void *ptr,
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int size)
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{
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extern unsigned long __xchg_bad_pointer(void);
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switch (size) {
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case 4:
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__asm__ __volatile__(
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" ex %0, [%1] \n"
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: "+r"(val)
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: "r"(ptr)
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: "memory");
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return val;
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}
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return __xchg_bad_pointer();
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}
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#define _xchg(ptr, with) ((typeof(*(ptr)))__xchg((unsigned long)(with), (ptr), \
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sizeof(*(ptr))))
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/*
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* On ARC700, EX insn is inherently atomic, so by default "vanilla" xchg() need
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* not require any locking. However there's a quirk.
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* ARC lacks native CMPXCHG, thus emulated (see above), using external locking -
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* incidently it "reuses" the same atomic_ops_lock used by atomic APIs.
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* Now, llist code uses cmpxchg() and xchg() on same data, so xchg() needs to
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* abide by same serializing rules, thus ends up using atomic_ops_lock as well.
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*
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* This however is only relevant if SMP and/or ARC lacks LLSC
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* if (UP or LLSC)
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* xchg doesn't need serialization
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* else <==> !(UP or LLSC) <==> (!UP and !LLSC) <==> (SMP and !LLSC)
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* xchg needs serialization
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*/
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#if !defined(CONFIG_ARC_HAS_LLSC) && defined(CONFIG_SMP)
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#define xchg(ptr, with) \
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({ \
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unsigned long flags; \
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typeof(*(ptr)) old_val; \
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\
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atomic_ops_lock(flags); \
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old_val = _xchg(ptr, with); \
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atomic_ops_unlock(flags); \
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old_val; \
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})
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#else
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#define xchg(ptr, with) _xchg(ptr, with)
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#endif
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/*
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* "atomic" variant of xchg()
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* REQ: It needs to follow the same serialization rules as other atomic_xxx()
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* Since xchg() doesn't always do that, it would seem that following defintion
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* is incorrect. But here's the rationale:
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* SMP : Even xchg() takes the atomic_ops_lock, so OK.
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* LLSC: atomic_ops_lock are not relevent at all (even if SMP, since LLSC
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* is natively "SMP safe", no serialization required).
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* UP : other atomics disable IRQ, so no way a difft ctxt atomic_xchg()
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* could clobber them. atomic_xchg() itself would be 1 insn, so it
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* can't be clobbered by others. Thus no serialization required when
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* atomic_xchg is involved.
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*/
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#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
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#endif
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