f907ab06bb
Conflicts: arch/arm/mach-lpc32xx/clock.c arch/arm/mach-pxa/pxa25x.c arch/arm/mach-pxa/pxa27x.c The conflicts with pxa are non-obvious, we have multiple branches adding and removing the same clock settings. According to Haojian Zhuang, removing the sa1100 rtc dummy clock is the correct fix here. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
141 lines
3.5 KiB
C
141 lines
3.5 KiB
C
/*
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* OMAP3/OMAP4 smartreflex device file
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*
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* Author: Thara Gopinath <thara@ti.com>
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*
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* Based originally on code from smartreflex.c
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* Copyright (C) 2010 Texas Instruments, Inc.
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* Thara Gopinath <thara@ti.com>
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*
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* Copyright (C) 2008 Nokia Corporation
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* Kalle Jokiniemi
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*
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* Copyright (C) 2007 Texas Instruments, Inc.
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* Lesly A M <x0080970@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/err.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <plat/omap_device.h>
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#include "smartreflex.h"
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#include "voltage.h"
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#include "control.h"
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#include "pm.h"
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static bool sr_enable_on_init;
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/* Read EFUSE values from control registers for OMAP3430 */
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static void __init sr_set_nvalues(struct omap_volt_data *volt_data,
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struct omap_sr_data *sr_data)
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{
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struct omap_sr_nvalue_table *nvalue_table;
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int i, count = 0;
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while (volt_data[count].volt_nominal)
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count++;
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nvalue_table = kzalloc(sizeof(struct omap_sr_nvalue_table)*count,
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GFP_KERNEL);
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for (i = 0; i < count; i++) {
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u32 v;
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/*
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* In OMAP4 the efuse registers are 24 bit aligned.
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* A __raw_readl will fail for non-32 bit aligned address
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* and hence the 8-bit read and shift.
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*/
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if (cpu_is_omap44xx()) {
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u16 offset = volt_data[i].sr_efuse_offs;
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v = omap_ctrl_readb(offset) |
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omap_ctrl_readb(offset + 1) << 8 |
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omap_ctrl_readb(offset + 2) << 16;
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} else {
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v = omap_ctrl_readl(volt_data[i].sr_efuse_offs);
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}
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nvalue_table[i].efuse_offs = volt_data[i].sr_efuse_offs;
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nvalue_table[i].nvalue = v;
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}
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sr_data->nvalue_table = nvalue_table;
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sr_data->nvalue_count = count;
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}
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static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
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{
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struct omap_sr_data *sr_data;
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struct platform_device *pdev;
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struct omap_volt_data *volt_data;
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struct omap_smartreflex_dev_attr *sr_dev_attr;
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char *name = "smartreflex";
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static int i;
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sr_data = kzalloc(sizeof(struct omap_sr_data), GFP_KERNEL);
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if (!sr_data) {
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pr_err("%s: Unable to allocate memory for %s sr_data.Error!\n",
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__func__, oh->name);
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return -ENOMEM;
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}
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sr_dev_attr = (struct omap_smartreflex_dev_attr *)oh->dev_attr;
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if (!sr_dev_attr || !sr_dev_attr->sensor_voltdm_name) {
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pr_err("%s: No voltage domain specified for %s."
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"Cannot initialize\n", __func__,
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oh->name);
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goto exit;
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}
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sr_data->ip_type = oh->class->rev;
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sr_data->senn_mod = 0x1;
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sr_data->senp_mod = 0x1;
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sr_data->voltdm = voltdm_lookup(sr_dev_attr->sensor_voltdm_name);
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if (IS_ERR(sr_data->voltdm)) {
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pr_err("%s: Unable to get voltage domain pointer for VDD %s\n",
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__func__, sr_dev_attr->sensor_voltdm_name);
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goto exit;
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}
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omap_voltage_get_volttable(sr_data->voltdm, &volt_data);
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if (!volt_data) {
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pr_warning("%s: No Voltage table registerd fo VDD%d."
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"Something really wrong\n\n", __func__, i + 1);
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goto exit;
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}
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sr_set_nvalues(volt_data, sr_data);
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sr_data->enable_on_init = sr_enable_on_init;
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pdev = omap_device_build(name, i, oh, sr_data, sizeof(*sr_data),
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NULL, 0, 0);
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if (IS_ERR(pdev))
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pr_warning("%s: Could not build omap_device for %s: %s.\n\n",
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__func__, name, oh->name);
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exit:
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i++;
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kfree(sr_data);
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return 0;
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}
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/*
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* API to be called from board files to enable smartreflex
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* autocompensation at init.
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*/
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void __init omap_enable_smartreflex_on_init(void)
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{
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sr_enable_on_init = true;
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}
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int __init omap_devinit_smartreflex(void)
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{
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return omap_hwmod_for_each_by_class("smartreflex", sr_dev_init, NULL);
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}
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