0282465320
This patch adds support for the global clock controller found on the APQ8084 based devices. This includes UART, I2C, SPI etc. Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
109 lines
3.3 KiB
C
109 lines
3.3 KiB
C
/*
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* Copyright (c) 2014, The Linux Foundation. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _DT_BINDINGS_RESET_APQ_GCC_8084_H
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#define _DT_BINDINGS_RESET_APQ_GCC_8084_H
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#define GCC_SYSTEM_NOC_BCR 0
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#define GCC_CONFIG_NOC_BCR 1
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#define GCC_PERIPH_NOC_BCR 2
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#define GCC_IMEM_BCR 3
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#define GCC_MMSS_BCR 4
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#define GCC_QDSS_BCR 5
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#define GCC_USB_30_BCR 6
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#define GCC_USB3_PHY_BCR 7
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#define GCC_USB_HS_HSIC_BCR 8
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#define GCC_USB_HS_BCR 9
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#define GCC_USB2A_PHY_BCR 10
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#define GCC_USB2B_PHY_BCR 11
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#define GCC_SDCC1_BCR 12
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#define GCC_SDCC2_BCR 13
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#define GCC_SDCC3_BCR 14
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#define GCC_SDCC4_BCR 15
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#define GCC_BLSP1_BCR 16
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#define GCC_BLSP1_QUP1_BCR 17
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#define GCC_BLSP1_UART1_BCR 18
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#define GCC_BLSP1_QUP2_BCR 19
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#define GCC_BLSP1_UART2_BCR 20
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#define GCC_BLSP1_QUP3_BCR 21
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#define GCC_BLSP1_UART3_BCR 22
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#define GCC_BLSP1_QUP4_BCR 23
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#define GCC_BLSP1_UART4_BCR 24
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#define GCC_BLSP1_QUP5_BCR 25
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#define GCC_BLSP1_UART5_BCR 26
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#define GCC_BLSP1_QUP6_BCR 27
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#define GCC_BLSP1_UART6_BCR 28
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#define GCC_BLSP2_BCR 29
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#define GCC_BLSP2_QUP1_BCR 30
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#define GCC_BLSP2_UART1_BCR 31
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#define GCC_BLSP2_QUP2_BCR 32
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#define GCC_BLSP2_UART2_BCR 33
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#define GCC_BLSP2_QUP3_BCR 34
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#define GCC_BLSP2_UART3_BCR 35
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#define GCC_BLSP2_QUP4_BCR 36
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#define GCC_BLSP2_UART4_BCR 37
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#define GCC_BLSP2_QUP5_BCR 38
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#define GCC_BLSP2_UART5_BCR 39
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#define GCC_BLSP2_QUP6_BCR 40
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#define GCC_BLSP2_UART6_BCR 41
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#define GCC_PDM_BCR 42
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#define GCC_PRNG_BCR 43
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#define GCC_BAM_DMA_BCR 44
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#define GCC_TSIF_BCR 45
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#define GCC_TCSR_BCR 46
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#define GCC_BOOT_ROM_BCR 47
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#define GCC_MSG_RAM_BCR 48
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#define GCC_TLMM_BCR 49
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#define GCC_MPM_BCR 50
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#define GCC_MPM_AHB_RESET 51
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#define GCC_MPM_NON_AHB_RESET 52
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#define GCC_SEC_CTRL_BCR 53
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#define GCC_SPMI_BCR 54
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#define GCC_SPDM_BCR 55
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#define GCC_CE1_BCR 56
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#define GCC_CE2_BCR 57
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#define GCC_BIMC_BCR 58
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#define GCC_SNOC_BUS_TIMEOUT0_BCR 59
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#define GCC_SNOC_BUS_TIMEOUT2_BCR 60
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#define GCC_PNOC_BUS_TIMEOUT0_BCR 61
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#define GCC_PNOC_BUS_TIMEOUT1_BCR 62
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#define GCC_PNOC_BUS_TIMEOUT2_BCR 63
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#define GCC_PNOC_BUS_TIMEOUT3_BCR 64
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#define GCC_PNOC_BUS_TIMEOUT4_BCR 65
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#define GCC_CNOC_BUS_TIMEOUT0_BCR 66
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#define GCC_CNOC_BUS_TIMEOUT1_BCR 67
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#define GCC_CNOC_BUS_TIMEOUT2_BCR 68
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#define GCC_CNOC_BUS_TIMEOUT3_BCR 69
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#define GCC_CNOC_BUS_TIMEOUT4_BCR 70
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#define GCC_CNOC_BUS_TIMEOUT5_BCR 71
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#define GCC_CNOC_BUS_TIMEOUT6_BCR 72
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#define GCC_DEHR_BCR 73
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#define GCC_RBCPR_BCR 74
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#define GCC_MSS_RESTART 75
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#define GCC_LPASS_RESTART 76
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#define GCC_WCSS_RESTART 77
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#define GCC_VENUS_RESTART 78
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#define GCC_COPSS_SMMU_BCR 79
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#define GCC_SPSS_BCR 80
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#define GCC_PCIE_0_BCR 81
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#define GCC_PCIE_0_PHY_BCR 82
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#define GCC_PCIE_1_BCR 83
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#define GCC_PCIE_1_PHY_BCR 84
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#define GCC_USB_30_SEC_BCR 85
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#define GCC_USB3_SEC_PHY_BCR 86
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#define GCC_SATA_BCR 87
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#define GCC_CE3_BCR 88
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#define GCC_UFS_BCR 89
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#define GCC_USB30_PHY_COM_BCR 90
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#endif
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