c5607d8e7a
Implement set_sysclk() and then rather than assuming 256fs use the supplied value to calculate and configure the clock ratio for the currently used sample rate. As a side effect we also end up implementing clock selection for the ADC path. In order to avoid confusion remove the existing set_clkdiv() based configuration of the clock source for the DAC and update the SMDK64xx driver (which is the only in-tree user of the CODEC). Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
35 lines
811 B
C
35 lines
811 B
C
/*
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* wm8580.h -- audio driver for WM8580
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*
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* Copyright 2008 Samsung Electronics.
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* Author: Ryu Euiyoul
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* ryu.real@gmail.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#ifndef _WM8580_H
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#define _WM8580_H
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#define WM8580_PLLA 1
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#define WM8580_PLLB 2
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#define WM8580_MCLK 1
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#define WM8580_CLKOUTSRC 2
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#define WM8580_CLKSRC_MCLK 1
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#define WM8580_CLKSRC_PLLA 2
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#define WM8580_CLKSRC_PLLB 3
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#define WM8580_CLKSRC_OSC 4
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#define WM8580_CLKSRC_NONE 5
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#define WM8580_CLKSRC_ADCMCLK 6
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#define WM8580_DAI_PAIFRX 0
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#define WM8580_DAI_PAIFTX 1
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#endif
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