For cpufreq example, it takes 13 steps (25 mV for one step) to increase vddcore from 0.95 V to 1.275 V, and the time of 64 clock cycles at 24 MHz for one step is ~2.67 uS, so the total delay time would be ~34.71 uS. But the current calculation in the driver gives 39 uS. Change the formula to have the addition of 1 be the last step, so that we can get a more precise delay time. For example above, the new formula will give 35 uS. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
		
			
				
	
	
		
			262 lines
		
	
	
	
		
			7.3 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			262 lines
		
	
	
	
		
			7.3 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
/*
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 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
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 */
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/*
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 * You should have received a copy of the GNU General Public License along
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 * with this program; if not, write to the Free Software Foundation, Inc.,
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 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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 */
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#include <linux/slab.h>
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#include <linux/device.h>
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#include <linux/module.h>
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#include <linux/mfd/syscon.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/regmap.h>
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#include <linux/regulator/driver.h>
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#include <linux/regulator/of_regulator.h>
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#define LDO_RAMP_UP_UNIT_IN_CYCLES      64 /* 64 cycles per step */
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#define LDO_RAMP_UP_FREQ_IN_MHZ         24 /* cycle based on 24M OSC */
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struct anatop_regulator {
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	const char *name;
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	u32 control_reg;
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	struct regmap *anatop;
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	int vol_bit_shift;
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	int vol_bit_width;
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	u32 delay_reg;
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	int delay_bit_shift;
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	int delay_bit_width;
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	int min_bit_val;
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	int min_voltage;
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	int max_voltage;
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	struct regulator_desc rdesc;
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	struct regulator_init_data *initdata;
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};
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static int anatop_regmap_set_voltage_sel(struct regulator_dev *reg,
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					unsigned selector)
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{
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	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
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	if (!anatop_reg->control_reg)
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		return -ENOTSUPP;
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	return regulator_set_voltage_sel_regmap(reg, selector);
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}
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static int anatop_regmap_set_voltage_time_sel(struct regulator_dev *reg,
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	unsigned int old_sel,
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	unsigned int new_sel)
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{
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	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
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	u32 val;
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	int ret = 0;
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	/* check whether need to care about LDO ramp up speed */
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	if (anatop_reg->delay_bit_width && new_sel > old_sel) {
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		/*
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		 * the delay for LDO ramp up time is
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		 * based on the register setting, we need
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		 * to calculate how many steps LDO need to
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		 * ramp up, and how much delay needed. (us)
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		 */
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		regmap_read(anatop_reg->anatop, anatop_reg->delay_reg, &val);
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		val = (val >> anatop_reg->delay_bit_shift) &
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			((1 << anatop_reg->delay_bit_width) - 1);
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		ret = (new_sel - old_sel) * (LDO_RAMP_UP_UNIT_IN_CYCLES <<
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			val) / LDO_RAMP_UP_FREQ_IN_MHZ + 1;
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	}
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	return ret;
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}
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static int anatop_regmap_get_voltage_sel(struct regulator_dev *reg)
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{
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	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
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	if (!anatop_reg->control_reg)
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		return -ENOTSUPP;
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	return regulator_get_voltage_sel_regmap(reg);
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}
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static struct regulator_ops anatop_rops = {
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	.set_voltage_sel = anatop_regmap_set_voltage_sel,
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	.set_voltage_time_sel = anatop_regmap_set_voltage_time_sel,
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	.get_voltage_sel = anatop_regmap_get_voltage_sel,
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	.list_voltage = regulator_list_voltage_linear,
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	.map_voltage = regulator_map_voltage_linear,
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};
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static int anatop_regulator_probe(struct platform_device *pdev)
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{
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	struct device *dev = &pdev->dev;
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	struct device_node *np = dev->of_node;
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	struct device_node *anatop_np;
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	struct regulator_desc *rdesc;
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	struct regulator_dev *rdev;
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	struct anatop_regulator *sreg;
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	struct regulator_init_data *initdata;
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	struct regulator_config config = { };
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	int ret = 0;
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	initdata = of_get_regulator_init_data(dev, np);
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	sreg = devm_kzalloc(dev, sizeof(*sreg), GFP_KERNEL);
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	if (!sreg)
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		return -ENOMEM;
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	sreg->initdata = initdata;
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	sreg->name = kstrdup(of_get_property(np, "regulator-name", NULL),
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			     GFP_KERNEL);
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	rdesc = &sreg->rdesc;
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	memset(rdesc, 0, sizeof(*rdesc));
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	rdesc->name = sreg->name;
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	rdesc->ops = &anatop_rops;
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	rdesc->type = REGULATOR_VOLTAGE;
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	rdesc->owner = THIS_MODULE;
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	anatop_np = of_get_parent(np);
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	if (!anatop_np)
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		return -ENODEV;
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	sreg->anatop = syscon_node_to_regmap(anatop_np);
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	of_node_put(anatop_np);
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	if (IS_ERR(sreg->anatop))
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		return PTR_ERR(sreg->anatop);
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	ret = of_property_read_u32(np, "anatop-reg-offset",
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				   &sreg->control_reg);
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	if (ret) {
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		dev_err(dev, "no anatop-reg-offset property set\n");
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		goto anatop_probe_end;
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	}
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	ret = of_property_read_u32(np, "anatop-vol-bit-width",
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				   &sreg->vol_bit_width);
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	if (ret) {
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		dev_err(dev, "no anatop-vol-bit-width property set\n");
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		goto anatop_probe_end;
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	}
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	ret = of_property_read_u32(np, "anatop-vol-bit-shift",
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				   &sreg->vol_bit_shift);
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	if (ret) {
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		dev_err(dev, "no anatop-vol-bit-shift property set\n");
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		goto anatop_probe_end;
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	}
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	ret = of_property_read_u32(np, "anatop-min-bit-val",
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				   &sreg->min_bit_val);
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	if (ret) {
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		dev_err(dev, "no anatop-min-bit-val property set\n");
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		goto anatop_probe_end;
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	}
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	ret = of_property_read_u32(np, "anatop-min-voltage",
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				   &sreg->min_voltage);
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	if (ret) {
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		dev_err(dev, "no anatop-min-voltage property set\n");
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		goto anatop_probe_end;
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	}
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	ret = of_property_read_u32(np, "anatop-max-voltage",
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				   &sreg->max_voltage);
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	if (ret) {
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		dev_err(dev, "no anatop-max-voltage property set\n");
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		goto anatop_probe_end;
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	}
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	/* read LDO ramp up setting, only for core reg */
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	of_property_read_u32(np, "anatop-delay-reg-offset",
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			     &sreg->delay_reg);
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	of_property_read_u32(np, "anatop-delay-bit-width",
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			     &sreg->delay_bit_width);
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	of_property_read_u32(np, "anatop-delay-bit-shift",
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			     &sreg->delay_bit_shift);
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	rdesc->n_voltages = (sreg->max_voltage - sreg->min_voltage) / 25000 + 1
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			    + sreg->min_bit_val;
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	rdesc->min_uV = sreg->min_voltage;
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	rdesc->uV_step = 25000;
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	rdesc->linear_min_sel = sreg->min_bit_val;
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	rdesc->vsel_reg = sreg->control_reg;
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	rdesc->vsel_mask = ((1 << sreg->vol_bit_width) - 1) <<
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			   sreg->vol_bit_shift;
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	config.dev = &pdev->dev;
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	config.init_data = initdata;
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	config.driver_data = sreg;
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	config.of_node = pdev->dev.of_node;
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	config.regmap = sreg->anatop;
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	/* register regulator */
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	rdev = regulator_register(rdesc, &config);
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	if (IS_ERR(rdev)) {
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		dev_err(dev, "failed to register %s\n",
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			rdesc->name);
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		ret = PTR_ERR(rdev);
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		goto anatop_probe_end;
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	}
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	platform_set_drvdata(pdev, rdev);
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anatop_probe_end:
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	if (ret)
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		kfree(sreg->name);
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	return ret;
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}
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static int anatop_regulator_remove(struct platform_device *pdev)
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{
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	struct regulator_dev *rdev = platform_get_drvdata(pdev);
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	struct anatop_regulator *sreg = rdev_get_drvdata(rdev);
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	const char *name = sreg->name;
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	regulator_unregister(rdev);
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	kfree(name);
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	return 0;
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}
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static struct of_device_id of_anatop_regulator_match_tbl[] = {
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	{ .compatible = "fsl,anatop-regulator", },
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	{ /* end */ }
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};
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static struct platform_driver anatop_regulator_driver = {
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	.driver = {
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		.name	= "anatop_regulator",
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		.owner  = THIS_MODULE,
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		.of_match_table = of_anatop_regulator_match_tbl,
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	},
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	.probe	= anatop_regulator_probe,
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	.remove	= anatop_regulator_remove,
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};
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static int __init anatop_regulator_init(void)
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{
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	return platform_driver_register(&anatop_regulator_driver);
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}
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postcore_initcall(anatop_regulator_init);
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static void __exit anatop_regulator_exit(void)
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{
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	platform_driver_unregister(&anatop_regulator_driver);
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}
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module_exit(anatop_regulator_exit);
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MODULE_AUTHOR("Nancy Chen <Nancy.Chen@freescale.com>, "
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	      "Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>");
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MODULE_DESCRIPTION("ANATOP Regulator driver");
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MODULE_LICENSE("GPL v2");
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