44922150d8
If we have a series of events from userpsace, with %fprs=FPRS_FEF, like follows: ETRAP ETRAP VIS_ENTRY(fprs=0x4) VIS_EXIT RTRAP (kernel FPU restore with fpu_saved=0x4) RTRAP We will not restore the user registers that were clobbered by the FPU using kernel code in the inner-most trap. Traps allocate FPU save slots in the thread struct, and FPU using sequences save the "dirty" FPU registers only. This works at the initial trap level because all of the registers get recorded into the top-level FPU save area, and we'll return to userspace with the FPU disabled so that any FPU use by the user will take an FPU disabled trap wherein we'll load the registers back up properly. But this is not how trap returns from kernel to kernel operate. The simplest fix for this bug is to always save all FPU register state for anything other than the top-most FPU save area. Getting rid of the optimized inner-slot FPU saving code ends up making VISEntryHalf degenerate into plain VISEntry. Longer term we need to do something smarter to reinstate the partial save optimizations. Perhaps the fundament error is having trap entry and exit allocate FPU save slots and restore register state. Instead, the VISEntry et al. calls should be doing that work. This bug is about two decades old. Reported-by: James Y Knight <jyknight@google.com> Signed-off-by: David S. Miller <davem@davemloft.net>
81 lines
1.7 KiB
ArmAsm
81 lines
1.7 KiB
ArmAsm
/*
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* VISsave.S: Code for saving FPU register state for
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* VIS routines. One should not call this directly,
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* but use macros provided in <asm/visasm.h>.
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*
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* Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
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*/
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#include <asm/asi.h>
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#include <asm/page.h>
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#include <asm/ptrace.h>
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#include <asm/visasm.h>
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#include <asm/thread_info.h>
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.text
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.globl VISenter, VISenterhalf
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/* On entry: %o5=current FPRS value, %g7 is callers address */
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/* May clobber %o5, %g1, %g2, %g3, %g7, %icc, %xcc */
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/* Nothing special need be done here to handle pre-emption, this
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* FPU save/restore mechanism is already preemption safe.
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*/
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.align 32
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VISenter:
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ldub [%g6 + TI_FPDEPTH], %g1
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brnz,a,pn %g1, 1f
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cmp %g1, 1
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stb %g0, [%g6 + TI_FPSAVED]
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stx %fsr, [%g6 + TI_XFSR]
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9: jmpl %g7 + %g0, %g0
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nop
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1: bne,pn %icc, 2f
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srl %g1, 1, %g1
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vis1: ldub [%g6 + TI_FPSAVED], %g3
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stx %fsr, [%g6 + TI_XFSR]
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or %g3, %o5, %g3
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stb %g3, [%g6 + TI_FPSAVED]
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rd %gsr, %g3
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clr %g1
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ba,pt %xcc, 3f
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stx %g3, [%g6 + TI_GSR]
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2: add %g6, %g1, %g3
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mov FPRS_DU | FPRS_DL | FPRS_FEF, %o5
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sll %g1, 3, %g1
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stb %o5, [%g3 + TI_FPSAVED]
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rd %gsr, %g2
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add %g6, %g1, %g3
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stx %g2, [%g3 + TI_GSR]
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add %g6, %g1, %g2
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stx %fsr, [%g2 + TI_XFSR]
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sll %g1, 5, %g1
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3: andcc %o5, FPRS_DL|FPRS_DU, %g0
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be,pn %icc, 9b
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add %g6, TI_FPREGS, %g2
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andcc %o5, FPRS_DL, %g0
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be,pn %icc, 4f
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add %g6, TI_FPREGS+0x40, %g3
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membar #Sync
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stda %f0, [%g2 + %g1] ASI_BLK_P
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stda %f16, [%g3 + %g1] ASI_BLK_P
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membar #Sync
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andcc %o5, FPRS_DU, %g0
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be,pn %icc, 5f
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4: add %g1, 128, %g1
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membar #Sync
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stda %f32, [%g2 + %g1] ASI_BLK_P
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stda %f48, [%g3 + %g1] ASI_BLK_P
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5: membar #Sync
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ba,pt %xcc, 80f
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nop
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.align 32
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80: jmpl %g7 + %g0, %g0
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nop
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