150 lines
4 KiB
C
150 lines
4 KiB
C
#include <linux/seq_file.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <asm/machvec.h>
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#include <asm/processor.h>
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static const char *cpu_name[] = {
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[CPU_SH7201] = "SH7201",
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[CPU_SH7203] = "SH7203", [CPU_SH7263] = "SH7263",
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[CPU_SH7264] = "SH7264", [CPU_SH7269] = "SH7269",
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[CPU_SH7206] = "SH7206", [CPU_SH7619] = "SH7619",
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[CPU_SH7705] = "SH7705", [CPU_SH7706] = "SH7706",
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[CPU_SH7707] = "SH7707", [CPU_SH7708] = "SH7708",
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[CPU_SH7709] = "SH7709", [CPU_SH7710] = "SH7710",
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[CPU_SH7712] = "SH7712", [CPU_SH7720] = "SH7720",
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[CPU_SH7721] = "SH7721", [CPU_SH7729] = "SH7729",
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[CPU_SH7750] = "SH7750", [CPU_SH7750S] = "SH7750S",
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[CPU_SH7750R] = "SH7750R", [CPU_SH7751] = "SH7751",
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[CPU_SH7751R] = "SH7751R", [CPU_SH7760] = "SH7760",
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[CPU_SH4_202] = "SH4-202", [CPU_SH4_501] = "SH4-501",
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[CPU_SH7763] = "SH7763", [CPU_SH7770] = "SH7770",
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[CPU_SH7780] = "SH7780", [CPU_SH7781] = "SH7781",
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[CPU_SH7343] = "SH7343", [CPU_SH7785] = "SH7785",
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[CPU_SH7786] = "SH7786", [CPU_SH7757] = "SH7757",
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[CPU_SH7722] = "SH7722", [CPU_SHX3] = "SH-X3",
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[CPU_SH5_101] = "SH5-101", [CPU_SH5_103] = "SH5-103",
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[CPU_MXG] = "MX-G", [CPU_SH7723] = "SH7723",
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[CPU_SH7366] = "SH7366", [CPU_SH7724] = "SH7724",
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[CPU_SH7372] = "SH7372", [CPU_SH7734] = "SH7734",
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[CPU_SH_NONE] = "Unknown"
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};
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const char *get_cpu_subtype(struct sh_cpuinfo *c)
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{
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return cpu_name[c->type];
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}
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EXPORT_SYMBOL(get_cpu_subtype);
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#ifdef CONFIG_PROC_FS
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/* Symbolic CPU flags, keep in sync with asm/cpu-features.h */
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static const char *cpu_flags[] = {
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"none", "fpu", "p2flush", "mmuassoc", "dsp", "perfctr",
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"ptea", "llsc", "l2", "op32", "pteaex", NULL
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};
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static void show_cpuflags(struct seq_file *m, struct sh_cpuinfo *c)
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{
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unsigned long i;
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seq_printf(m, "cpu flags\t:");
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if (!c->flags) {
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seq_printf(m, " %s\n", cpu_flags[0]);
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return;
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}
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for (i = 0; cpu_flags[i]; i++)
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if ((c->flags & (1 << i)))
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seq_printf(m, " %s", cpu_flags[i+1]);
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seq_printf(m, "\n");
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}
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static void show_cacheinfo(struct seq_file *m, const char *type,
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struct cache_info info)
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{
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unsigned int cache_size;
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cache_size = info.ways * info.sets * info.linesz;
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seq_printf(m, "%s size\t: %2dKiB (%d-way)\n",
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type, cache_size >> 10, info.ways);
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}
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/*
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* Get CPU information for use by the procfs.
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*/
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static int show_cpuinfo(struct seq_file *m, void *v)
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{
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struct sh_cpuinfo *c = v;
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unsigned int cpu = c - cpu_data;
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if (!cpu_online(cpu))
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return 0;
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if (cpu == 0)
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seq_printf(m, "machine\t\t: %s\n", get_system_type());
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else
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seq_printf(m, "\n");
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seq_printf(m, "processor\t: %d\n", cpu);
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seq_printf(m, "cpu family\t: %s\n", init_utsname()->machine);
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seq_printf(m, "cpu type\t: %s\n", get_cpu_subtype(c));
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if (c->cut_major == -1)
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seq_printf(m, "cut\t\t: unknown\n");
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else if (c->cut_minor == -1)
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seq_printf(m, "cut\t\t: %d.x\n", c->cut_major);
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else
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seq_printf(m, "cut\t\t: %d.%d\n", c->cut_major, c->cut_minor);
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show_cpuflags(m, c);
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seq_printf(m, "cache type\t: ");
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/*
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* Check for what type of cache we have, we support both the
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* unified cache on the SH-2 and SH-3, as well as the harvard
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* style cache on the SH-4.
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*/
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if (c->icache.flags & SH_CACHE_COMBINED) {
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seq_printf(m, "unified\n");
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show_cacheinfo(m, "cache", c->icache);
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} else {
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seq_printf(m, "split (harvard)\n");
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show_cacheinfo(m, "icache", c->icache);
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show_cacheinfo(m, "dcache", c->dcache);
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}
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/* Optional secondary cache */
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if (c->flags & CPU_HAS_L2_CACHE)
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show_cacheinfo(m, "scache", c->scache);
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seq_printf(m, "address sizes\t: %u bits physical\n", c->phys_bits);
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seq_printf(m, "bogomips\t: %lu.%02lu\n",
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c->loops_per_jiffy/(500000/HZ),
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(c->loops_per_jiffy/(5000/HZ)) % 100);
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return 0;
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}
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static void *c_start(struct seq_file *m, loff_t *pos)
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{
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return *pos < NR_CPUS ? cpu_data + *pos : NULL;
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}
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static void *c_next(struct seq_file *m, void *v, loff_t *pos)
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{
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++*pos;
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return c_start(m, pos);
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}
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static void c_stop(struct seq_file *m, void *v)
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{
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}
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const struct seq_operations cpuinfo_op = {
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.start = c_start,
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.next = c_next,
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.stop = c_stop,
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.show = show_cpuinfo,
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};
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#endif /* CONFIG_PROC_FS */
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