b92b8b35a2
Since set_mb() is really about an smp_mb() -- not a IO/DMA barrier like mb() rename it to match the recent smp_load_acquire() and smp_store_release(). Suggested-by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
150 lines
3.7 KiB
C
150 lines
3.7 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2006 by Ralf Baechle (ralf@linux-mips.org)
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*/
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#ifndef __ASM_BARRIER_H
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#define __ASM_BARRIER_H
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#include <asm/addrspace.h>
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#define read_barrier_depends() do { } while(0)
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#define smp_read_barrier_depends() do { } while(0)
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#ifdef CONFIG_CPU_HAS_SYNC
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#define __sync() \
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__asm__ __volatile__( \
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".set push\n\t" \
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".set noreorder\n\t" \
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".set mips2\n\t" \
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"sync\n\t" \
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".set pop" \
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: /* no output */ \
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: /* no input */ \
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: "memory")
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#else
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#define __sync() do { } while(0)
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#endif
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#define __fast_iob() \
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__asm__ __volatile__( \
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".set push\n\t" \
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".set noreorder\n\t" \
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"lw $0,%0\n\t" \
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"nop\n\t" \
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".set pop" \
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: /* no output */ \
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: "m" (*(int *)CKSEG1) \
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: "memory")
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#ifdef CONFIG_CPU_CAVIUM_OCTEON
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# define OCTEON_SYNCW_STR ".set push\n.set arch=octeon\nsyncw\nsyncw\n.set pop\n"
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# define __syncw() __asm__ __volatile__(OCTEON_SYNCW_STR : : : "memory")
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# define fast_wmb() __syncw()
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# define fast_rmb() barrier()
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# define fast_mb() __sync()
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# define fast_iob() do { } while (0)
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#else /* ! CONFIG_CPU_CAVIUM_OCTEON */
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# define fast_wmb() __sync()
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# define fast_rmb() __sync()
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# define fast_mb() __sync()
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# ifdef CONFIG_SGI_IP28
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# define fast_iob() \
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__asm__ __volatile__( \
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".set push\n\t" \
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".set noreorder\n\t" \
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"lw $0,%0\n\t" \
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"sync\n\t" \
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"lw $0,%0\n\t" \
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".set pop" \
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: /* no output */ \
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: "m" (*(int *)CKSEG1ADDR(0x1fa00004)) \
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: "memory")
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# else
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# define fast_iob() \
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do { \
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__sync(); \
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__fast_iob(); \
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} while (0)
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# endif
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#endif /* CONFIG_CPU_CAVIUM_OCTEON */
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#ifdef CONFIG_CPU_HAS_WB
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#include <asm/wbflush.h>
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#define mb() wbflush()
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#define iob() wbflush()
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#else /* !CONFIG_CPU_HAS_WB */
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#define mb() fast_mb()
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#define iob() fast_iob()
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#endif /* !CONFIG_CPU_HAS_WB */
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#define wmb() fast_wmb()
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#define rmb() fast_rmb()
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#define dma_wmb() fast_wmb()
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#define dma_rmb() fast_rmb()
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#if defined(CONFIG_WEAK_ORDERING) && defined(CONFIG_SMP)
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# ifdef CONFIG_CPU_CAVIUM_OCTEON
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# define smp_mb() __sync()
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# define smp_rmb() barrier()
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# define smp_wmb() __syncw()
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# else
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# define smp_mb() __asm__ __volatile__("sync" : : :"memory")
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# define smp_rmb() __asm__ __volatile__("sync" : : :"memory")
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# define smp_wmb() __asm__ __volatile__("sync" : : :"memory")
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# endif
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#else
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#endif
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#if defined(CONFIG_WEAK_REORDERING_BEYOND_LLSC) && defined(CONFIG_SMP)
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#define __WEAK_LLSC_MB " sync \n"
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#else
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#define __WEAK_LLSC_MB " \n"
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#endif
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#define smp_store_mb(var, value) \
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do { WRITE_ONCE(var, value); smp_mb(); } while (0)
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#define smp_llsc_mb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
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#ifdef CONFIG_CPU_CAVIUM_OCTEON
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#define smp_mb__before_llsc() smp_wmb()
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/* Cause previous writes to become visible on all CPUs as soon as possible */
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#define nudge_writes() __asm__ __volatile__(".set push\n\t" \
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".set arch=octeon\n\t" \
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"syncw\n\t" \
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".set pop" : : : "memory")
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#else
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#define smp_mb__before_llsc() smp_llsc_mb()
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#define nudge_writes() mb()
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#endif
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#define smp_store_release(p, v) \
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do { \
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compiletime_assert_atomic_type(*p); \
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smp_mb(); \
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ACCESS_ONCE(*p) = (v); \
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} while (0)
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#define smp_load_acquire(p) \
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({ \
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typeof(*p) ___p1 = ACCESS_ONCE(*p); \
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compiletime_assert_atomic_type(*p); \
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smp_mb(); \
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___p1; \
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})
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#define smp_mb__before_atomic() smp_mb__before_llsc()
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#define smp_mb__after_atomic() smp_llsc_mb()
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#endif /* __ASM_BARRIER_H */
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