c9034c3a1d
Disintegrate asm/system.h for M32R. Signed-off-by: David Howells <dhowells@redhat.com> cc: linux-m32r@ml.linux-m32r.org
113 lines
2.6 KiB
C
113 lines
2.6 KiB
C
/*
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* linux/arch/m32r/platforms/oaks32r/setup.c
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*
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* Setup routines for OAKS32R Board
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*
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* Copyright (c) 2002-2005 Hiroyuki Kondo, Hirokazu Takata,
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* Hitoshi Yamamoto, Mamoru Sakugawa
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*/
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <asm/m32r.h>
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#include <asm/io.h>
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#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
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icu_data_t icu_data[NR_IRQS];
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static void disable_oaks32r_irq(unsigned int irq)
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{
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unsigned long port, data;
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port = irq2port(irq);
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data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
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outl(data, port);
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}
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static void enable_oaks32r_irq(unsigned int irq)
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{
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unsigned long port, data;
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port = irq2port(irq);
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data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
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outl(data, port);
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}
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static void mask_oaks32r(struct irq_data *data)
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{
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disable_oaks32r_irq(data->irq);
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}
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static void unmask_oaks32r(struct irq_data *data)
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{
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enable_oaks32r_irq(data->irq);
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}
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static void shutdown_oaks32r(struct irq_data *data)
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{
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unsigned long port;
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port = irq2port(data->irq);
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outl(M32R_ICUCR_ILEVEL7, port);
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}
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static struct irq_chip oaks32r_irq_type =
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{
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.name = "OAKS32R-IRQ",
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.irq_shutdown = shutdown_oaks32r,
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.irq_mask = mask_oaks32r,
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.irq_unmask = unmask_oaks32r,
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};
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void __init init_IRQ(void)
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{
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static int once = 0;
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if (once)
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return;
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else
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once++;
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#ifdef CONFIG_NE2000
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/* INT3 : LAN controller (RTL8019AS) */
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irq_set_chip_and_handler(M32R_IRQ_INT3, &oaks32r_irq_type,
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handle_level_irq);
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icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
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disable_oaks32r_irq(M32R_IRQ_INT3);
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#endif /* CONFIG_M32R_NE2000 */
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/* MFT2 : system timer */
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irq_set_chip_and_handler(M32R_IRQ_MFT2, &oaks32r_irq_type,
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handle_level_irq);
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icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
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disable_oaks32r_irq(M32R_IRQ_MFT2);
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#ifdef CONFIG_SERIAL_M32R_SIO
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/* SIO0_R : uart receive data */
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irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &oaks32r_irq_type,
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handle_level_irq);
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icu_data[M32R_IRQ_SIO0_R].icucr = 0;
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disable_oaks32r_irq(M32R_IRQ_SIO0_R);
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/* SIO0_S : uart send data */
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irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &oaks32r_irq_type,
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handle_level_irq);
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icu_data[M32R_IRQ_SIO0_S].icucr = 0;
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disable_oaks32r_irq(M32R_IRQ_SIO0_S);
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/* SIO1_R : uart receive data */
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irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &oaks32r_irq_type,
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handle_level_irq);
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icu_data[M32R_IRQ_SIO1_R].icucr = 0;
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disable_oaks32r_irq(M32R_IRQ_SIO1_R);
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/* SIO1_S : uart send data */
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irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &oaks32r_irq_type,
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handle_level_irq);
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icu_data[M32R_IRQ_SIO1_S].icucr = 0;
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disable_oaks32r_irq(M32R_IRQ_SIO1_S);
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#endif /* CONFIG_SERIAL_M32R_SIO */
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}
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