6ebbf2ce43
ARMv6 and greater introduced a new instruction ("bx") which can be used
to return from function calls. Recent CPUs perform better when the
"bx lr" instruction is used rather than the "mov pc, lr" instruction,
and this sequence is strongly recommended to be used by the ARM
architecture manual (section A.4.1.1).
We provide a new macro "ret" with all its variants for the condition
code which will resolve to the appropriate instruction.
Rather than doing this piecemeal, and miss some instances, change all
the "mov pc" instances to use the new macro, with the exception of
the "movs" instruction and the kprobes code. This allows us to detect
the "mov pc, lr" case and fix it up - and also gives us the possibility
of deploying this for other registers depending on the CPU selection.
Reported-by: Will Deacon <will.deacon@arm.com>
Tested-by: Stephen Warren <swarren@nvidia.com> # Tegra Jetson TK1
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> # mioa701_bootresume.S
Tested-by: Andrew Lunn <andrew@lunn.ch> # Kirkwood
Tested-by: Shawn Guo <shawn.guo@freescale.com>
Tested-by: Tony Lindgren <tony@atomide.com> # OMAPs
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com> # Armada XP, 375, 385
Acked-by: Sekhar Nori <nsekhar@ti.com> # DaVinci
Acked-by: Christoffer Dall <christoffer.dall@linaro.org> # kvm/hyp
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> # PXA3xx
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> # Xen
Tested-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> # ARMv7M
Tested-by: Simon Horman <horms+renesas@verge.net.au> # Shmobile
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
150 lines
3.2 KiB
ArmAsm
150 lines
3.2 KiB
ArmAsm
/*
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* linux/arch/arm/mm/cache-v4.S
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*
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* Copyright (C) 1997-2002 Russell king
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/page.h>
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#include "proc-macros.S"
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/*
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* flush_icache_all()
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*
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* Unconditionally clean and invalidate the entire icache.
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*/
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ENTRY(v4_flush_icache_all)
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ret lr
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ENDPROC(v4_flush_icache_all)
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/*
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* flush_user_cache_all()
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*
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* Invalidate all cache entries in a particular address
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* space.
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*
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* - mm - mm_struct describing address space
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*/
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ENTRY(v4_flush_user_cache_all)
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/* FALLTHROUGH */
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/*
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* flush_kern_cache_all()
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*
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* Clean and invalidate the entire cache.
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*/
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ENTRY(v4_flush_kern_cache_all)
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#ifdef CONFIG_CPU_CP15
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mov r0, #0
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mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
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ret lr
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#else
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/* FALLTHROUGH */
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#endif
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/*
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* flush_user_cache_range(start, end, flags)
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*
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* Invalidate a range of cache entries in the specified
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* address space.
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*
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* - start - start address (may not be aligned)
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* - end - end address (exclusive, may not be aligned)
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* - flags - vma_area_struct flags describing address space
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*/
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ENTRY(v4_flush_user_cache_range)
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#ifdef CONFIG_CPU_CP15
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mov ip, #0
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mcr p15, 0, ip, c7, c7, 0 @ flush ID cache
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ret lr
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#else
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/* FALLTHROUGH */
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#endif
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/*
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* coherent_kern_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(v4_coherent_kern_range)
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/* FALLTHROUGH */
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/*
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* coherent_user_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(v4_coherent_user_range)
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mov r0, #0
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ret lr
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/*
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* flush_kern_dcache_area(void *addr, size_t size)
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*
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* Ensure no D cache aliasing occurs, either with itself or
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* the I cache
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*
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* - addr - kernel address
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* - size - region size
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*/
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ENTRY(v4_flush_kern_dcache_area)
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/* FALLTHROUGH */
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/*
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* dma_flush_range(start, end)
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*
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* Clean and invalidate the specified virtual address range.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(v4_dma_flush_range)
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#ifdef CONFIG_CPU_CP15
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mov r0, #0
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mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
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#endif
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ret lr
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/*
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* dma_unmap_area(start, size, dir)
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* - start - kernel virtual start address
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* - size - size of region
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* - dir - DMA direction
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*/
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ENTRY(v4_dma_unmap_area)
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teq r2, #DMA_TO_DEVICE
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bne v4_dma_flush_range
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/* FALLTHROUGH */
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/*
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* dma_map_area(start, size, dir)
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* - start - kernel virtual start address
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* - size - size of region
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* - dir - DMA direction
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*/
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ENTRY(v4_dma_map_area)
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ret lr
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ENDPROC(v4_dma_unmap_area)
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ENDPROC(v4_dma_map_area)
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.globl v4_flush_kern_cache_louis
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.equ v4_flush_kern_cache_louis, v4_flush_kern_cache_all
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__INITDATA
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@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
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define_cache_functions v4
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