bbb33445b9
CP_INTC code in entry-macro.S code reads SECR1n register to see if an interrupt was indeed pending. This register is actually marked as write-only in the OMAP-L138 TRM. Moreover, the code just checks to see the entire register is non-zero and does not check a specific interrupt number. Fix this to use interrupt pending bit in GIPR register for this purpose. GIPR register is already being read to know the highest priority interrupt pending. Signed-off-by: Sekhar Nori <nsekhar@ti.com>
39 lines
1 KiB
ArmAsm
39 lines
1 KiB
ArmAsm
/*
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* Low-level IRQ helper macros for TI DaVinci-based platforms
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*
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* Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
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*
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* 2007 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <mach/irqs.h>
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.macro get_irqnr_preamble, base, tmp
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ldr \base, =davinci_intc_base
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ldr \base, [\base]
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.endm
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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#if defined(CONFIG_AINTC) && defined(CONFIG_CP_INTC)
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ldr \tmp, =davinci_intc_type
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ldr \tmp, [\tmp]
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cmp \tmp, #DAVINCI_INTC_TYPE_CP_INTC
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beq 1001f
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#endif
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#if defined(CONFIG_AINTC)
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ldr \tmp, [\base, #0x14]
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movs \tmp, \tmp, lsr #2
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sub \irqnr, \tmp, #1
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b 1002f
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#endif
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#if defined(CONFIG_CP_INTC)
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1001: ldr \irqnr, [\base, #0x80] /* get irq number */
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mov \tmp, \irqnr, lsr #31
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and \irqnr, \irqnr, #0xff /* irq is in bits 0-9 */
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and \tmp, \tmp, #0x1
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cmp \tmp, #0x1
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#endif
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1002:
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.endm
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