6ebbf2ce43
ARMv6 and greater introduced a new instruction ("bx") which can be used
to return from function calls. Recent CPUs perform better when the
"bx lr" instruction is used rather than the "mov pc, lr" instruction,
and this sequence is strongly recommended to be used by the ARM
architecture manual (section A.4.1.1).
We provide a new macro "ret" with all its variants for the condition
code which will resolve to the appropriate instruction.
Rather than doing this piecemeal, and miss some instances, change all
the "mov pc" instances to use the new macro, with the exception of
the "movs" instruction and the kprobes code. This allows us to detect
the "mov pc, lr" case and fix it up - and also gives us the possibility
of deploying this for other registers depending on the CPU selection.
Reported-by: Will Deacon <will.deacon@arm.com>
Tested-by: Stephen Warren <swarren@nvidia.com> # Tegra Jetson TK1
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> # mioa701_bootresume.S
Tested-by: Andrew Lunn <andrew@lunn.ch> # Kirkwood
Tested-by: Shawn Guo <shawn.guo@freescale.com>
Tested-by: Tony Lindgren <tony@atomide.com> # OMAPs
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com> # Armada XP, 375, 385
Acked-by: Sekhar Nori <nsekhar@ti.com> # DaVinci
Acked-by: Christoffer Dall <christoffer.dall@linaro.org> # kvm/hyp
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> # PXA3xx
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> # Xen
Tested-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> # ARMv7M
Tested-by: Simon Horman <horms+renesas@verge.net.au> # Shmobile
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
212 lines
4 KiB
ArmAsm
212 lines
4 KiB
ArmAsm
/*
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* linux/arch/arm/lib/div64.S
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*
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* Optimized computation of 64-bit dividend / 32-bit divisor
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*
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* Author: Nicolas Pitre
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* Created: Oct 5, 2003
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* Copyright: Monta Vista Software, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/unwind.h>
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#ifdef __ARMEB__
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#define xh r0
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#define xl r1
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#define yh r2
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#define yl r3
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#else
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#define xl r0
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#define xh r1
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#define yl r2
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#define yh r3
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#endif
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/*
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* __do_div64: perform a division with 64-bit dividend and 32-bit divisor.
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*
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* Note: Calling convention is totally non standard for optimal code.
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* This is meant to be used by do_div() from include/asm/div64.h only.
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*
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* Input parameters:
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* xh-xl = dividend (clobbered)
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* r4 = divisor (preserved)
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*
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* Output values:
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* yh-yl = result
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* xh = remainder
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*
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* Clobbered regs: xl, ip
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*/
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ENTRY(__do_div64)
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UNWIND(.fnstart)
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@ Test for easy paths first.
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subs ip, r4, #1
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bls 9f @ divisor is 0 or 1
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tst ip, r4
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beq 8f @ divisor is power of 2
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@ See if we need to handle upper 32-bit result.
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cmp xh, r4
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mov yh, #0
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blo 3f
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@ Align divisor with upper part of dividend.
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@ The aligned divisor is stored in yl preserving the original.
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@ The bit position is stored in ip.
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#if __LINUX_ARM_ARCH__ >= 5
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clz yl, r4
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clz ip, xh
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sub yl, yl, ip
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mov ip, #1
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mov ip, ip, lsl yl
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mov yl, r4, lsl yl
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#else
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mov yl, r4
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mov ip, #1
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1: cmp yl, #0x80000000
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cmpcc yl, xh
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movcc yl, yl, lsl #1
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movcc ip, ip, lsl #1
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bcc 1b
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#endif
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@ The division loop for needed upper bit positions.
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@ Break out early if dividend reaches 0.
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2: cmp xh, yl
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orrcs yh, yh, ip
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subcss xh, xh, yl
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movnes ip, ip, lsr #1
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mov yl, yl, lsr #1
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bne 2b
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@ See if we need to handle lower 32-bit result.
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3: cmp xh, #0
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mov yl, #0
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cmpeq xl, r4
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movlo xh, xl
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retlo lr
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@ The division loop for lower bit positions.
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@ Here we shift remainer bits leftwards rather than moving the
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@ divisor for comparisons, considering the carry-out bit as well.
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mov ip, #0x80000000
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4: movs xl, xl, lsl #1
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adcs xh, xh, xh
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beq 6f
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cmpcc xh, r4
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5: orrcs yl, yl, ip
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subcs xh, xh, r4
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movs ip, ip, lsr #1
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bne 4b
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ret lr
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@ The top part of remainder became zero. If carry is set
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@ (the 33th bit) this is a false positive so resume the loop.
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@ Otherwise, if lower part is also null then we are done.
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6: bcs 5b
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cmp xl, #0
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reteq lr
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@ We still have remainer bits in the low part. Bring them up.
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#if __LINUX_ARM_ARCH__ >= 5
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clz xh, xl @ we know xh is zero here so...
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add xh, xh, #1
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mov xl, xl, lsl xh
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mov ip, ip, lsr xh
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#else
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7: movs xl, xl, lsl #1
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mov ip, ip, lsr #1
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bcc 7b
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#endif
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@ Current remainder is now 1. It is worthless to compare with
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@ divisor at this point since divisor can not be smaller than 3 here.
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@ If possible, branch for another shift in the division loop.
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@ If no bit position left then we are done.
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movs ip, ip, lsr #1
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mov xh, #1
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bne 4b
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ret lr
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8: @ Division by a power of 2: determine what that divisor order is
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@ then simply shift values around
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#if __LINUX_ARM_ARCH__ >= 5
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clz ip, r4
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rsb ip, ip, #31
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#else
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mov yl, r4
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cmp r4, #(1 << 16)
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mov ip, #0
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movhs yl, yl, lsr #16
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movhs ip, #16
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cmp yl, #(1 << 8)
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movhs yl, yl, lsr #8
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addhs ip, ip, #8
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cmp yl, #(1 << 4)
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movhs yl, yl, lsr #4
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addhs ip, ip, #4
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cmp yl, #(1 << 2)
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addhi ip, ip, #3
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addls ip, ip, yl, lsr #1
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#endif
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mov yh, xh, lsr ip
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mov yl, xl, lsr ip
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rsb ip, ip, #32
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ARM( orr yl, yl, xh, lsl ip )
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THUMB( lsl xh, xh, ip )
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THUMB( orr yl, yl, xh )
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mov xh, xl, lsl ip
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mov xh, xh, lsr ip
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ret lr
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@ eq -> division by 1: obvious enough...
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9: moveq yl, xl
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moveq yh, xh
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moveq xh, #0
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reteq lr
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UNWIND(.fnend)
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UNWIND(.fnstart)
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UNWIND(.pad #4)
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UNWIND(.save {lr})
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Ldiv0_64:
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@ Division by 0:
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str lr, [sp, #-8]!
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bl __div0
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@ as wrong as it could be...
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mov yl, #0
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mov yh, #0
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mov xh, #0
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ldr pc, [sp], #8
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UNWIND(.fnend)
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ENDPROC(__do_div64)
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