4b8f7a11c9
Instantiate the L2 cache from DT. Indicate in DT where the cache control register is so that it is possible to enable/disable write through on the CPU. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
13 lines
398 B
C
13 lines
398 B
C
/*
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* arch/arm/include/asm/hardware/cache-feroceon-l2.h
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*
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* Copyright (C) 2008 Marvell Semiconductor
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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extern void __init feroceon_l2_init(int l2_wt_override);
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extern int __init feroceon_of_init(void);
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