795f455856
L2 cache on ARCHS processors is called SLC (System Level Cache) For working DMA (in absence of hardware assisted IO Coherency) we need to manage SLC explicitly when buffers transition between cpu and controllers. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
97 lines
2.6 KiB
C
97 lines
2.6 KiB
C
/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ARC_ASM_CACHE_H
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#define __ARC_ASM_CACHE_H
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/* In case $$ not config, setup a dummy number for rest of kernel */
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#ifndef CONFIG_ARC_CACHE_LINE_SHIFT
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#define L1_CACHE_SHIFT 6
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#else
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#define L1_CACHE_SHIFT CONFIG_ARC_CACHE_LINE_SHIFT
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#endif
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#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
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#define CACHE_LINE_MASK (~(L1_CACHE_BYTES - 1))
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/*
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* ARC700 doesn't cache any access in top 1G (0xc000_0000 to 0xFFFF_FFFF)
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* Ideal for wiring memory mapped peripherals as we don't need to do
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* explicit uncached accesses (LD.di/ST.di) hence more portable drivers
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*/
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#define ARC_UNCACHED_ADDR_SPACE 0xc0000000
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#ifndef __ASSEMBLY__
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/* Uncached access macros */
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#define arc_read_uncached_32(ptr) \
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({ \
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unsigned int __ret; \
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__asm__ __volatile__( \
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" ld.di %0, [%1] \n" \
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: "=r"(__ret) \
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: "r"(ptr)); \
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__ret; \
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})
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#define arc_write_uncached_32(ptr, data)\
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({ \
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__asm__ __volatile__( \
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" st.di %0, [%1] \n" \
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: \
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: "r"(data), "r"(ptr)); \
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})
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#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
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extern void arc_cache_init(void);
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extern char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len);
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extern void read_decode_cache_bcr(void);
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#endif /* !__ASSEMBLY__ */
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/* Instruction cache related Auxiliary registers */
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#define ARC_REG_IC_BCR 0x77 /* Build Config reg */
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#define ARC_REG_IC_IVIC 0x10
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#define ARC_REG_IC_CTRL 0x11
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#define ARC_REG_IC_IVIL 0x19
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#if defined(CONFIG_ARC_MMU_V3) || defined(CONFIG_ARC_MMU_V4)
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#define ARC_REG_IC_PTAG 0x1E
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#endif
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/* Bit val in IC_CTRL */
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#define IC_CTRL_CACHE_DISABLE 0x1
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/* Data cache related Auxiliary registers */
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#define ARC_REG_DC_BCR 0x72 /* Build Config reg */
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#define ARC_REG_DC_IVDC 0x47
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#define ARC_REG_DC_CTRL 0x48
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#define ARC_REG_DC_IVDL 0x4A
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#define ARC_REG_DC_FLSH 0x4B
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#define ARC_REG_DC_FLDL 0x4C
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#define ARC_REG_DC_PTAG 0x5C
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/* Bit val in DC_CTRL */
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#define DC_CTRL_INV_MODE_FLUSH 0x40
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#define DC_CTRL_FLUSH_STATUS 0x100
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/*System-level cache (L2 cache) related Auxiliary registers */
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#define ARC_REG_SLC_CFG 0x901
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#define ARC_REG_SLC_CTRL 0x903
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#define ARC_REG_SLC_FLUSH 0x904
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#define ARC_REG_SLC_INVALIDATE 0x905
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#define ARC_REG_SLC_RGN_START 0x914
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#define ARC_REG_SLC_RGN_END 0x916
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/* Bit val in SLC_CONTROL */
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#define SLC_CTRL_IM 0x040
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#define SLC_CTRL_DISABLE 0x001
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#define SLC_CTRL_BUSY 0x100
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#define SLC_CTRL_RGN_OP_INV 0x200
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#endif /* _ASM_CACHE_H */
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