156 lines
4 KiB
C
156 lines
4 KiB
C
/*
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* linux/arch/arm/plat-versatile/timer-sp.c
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*
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* Copyright (C) 1999 - 2003 ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <asm/hardware/arm_timer.h>
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#include <plat/timer-sp.h>
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/*
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* These timers are currently always setup to be clocked at 1MHz.
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*/
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#define TIMER_FREQ_KHZ (1000)
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#define TIMER_RELOAD (TIMER_FREQ_KHZ * 1000 / HZ)
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static void __iomem *clksrc_base;
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static cycle_t sp804_read(struct clocksource *cs)
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{
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return ~readl(clksrc_base + TIMER_VALUE);
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}
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static struct clocksource clocksource_sp804 = {
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.name = "timer3",
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.rating = 200,
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.read = sp804_read,
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.mask = CLOCKSOURCE_MASK(32),
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.shift = 20,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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void __init sp804_clocksource_init(void __iomem *base)
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{
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struct clocksource *cs = &clocksource_sp804;
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clksrc_base = base;
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/* setup timer 0 as free-running clocksource */
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writel(0, clksrc_base + TIMER_CTRL);
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writel(0xffffffff, clksrc_base + TIMER_LOAD);
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writel(0xffffffff, clksrc_base + TIMER_VALUE);
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writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
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clksrc_base + TIMER_CTRL);
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cs->mult = clocksource_khz2mult(TIMER_FREQ_KHZ, cs->shift);
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clocksource_register(cs);
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}
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static void __iomem *clkevt_base;
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/*
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* IRQ handler for the timer
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*/
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static irqreturn_t sp804_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = dev_id;
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/* clear the interrupt */
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writel(1, clkevt_base + TIMER_INTCLR);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static void sp804_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE;
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writel(ctrl, clkevt_base + TIMER_CTRL);
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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writel(TIMER_RELOAD, clkevt_base + TIMER_LOAD);
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ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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/* period set, and timer enabled in 'next_event' hook */
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ctrl |= TIMER_CTRL_ONESHOT;
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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default:
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break;
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}
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writel(ctrl, clkevt_base + TIMER_CTRL);
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}
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static int sp804_set_next_event(unsigned long next,
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struct clock_event_device *evt)
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{
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unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
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writel(next, clkevt_base + TIMER_LOAD);
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writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
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return 0;
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}
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static struct clock_event_device sp804_clockevent = {
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.name = "timer0",
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.shift = 32,
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_mode = sp804_set_mode,
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.set_next_event = sp804_set_next_event,
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.rating = 300,
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.cpumask = cpu_all_mask,
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};
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static struct irqaction sp804_timer_irq = {
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.name = "timer",
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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.handler = sp804_timer_interrupt,
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.dev_id = &sp804_clockevent,
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};
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void __init sp804_clockevents_init(void __iomem *base, unsigned int timer_irq)
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{
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struct clock_event_device *evt = &sp804_clockevent;
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clkevt_base = base;
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evt->irq = timer_irq;
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evt->mult = div_sc(TIMER_FREQ_KHZ, NSEC_PER_MSEC, evt->shift);
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evt->max_delta_ns = clockevent_delta2ns(0xffffffff, evt);
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evt->min_delta_ns = clockevent_delta2ns(0xf, evt);
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setup_irq(timer_irq, &sp804_timer_irq);
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clockevents_register_device(evt);
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}
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