The OMAP2 MPU virtual clock node code attempted to call clk_get_rate() while the clockfw_lock spinlock was held. Fix by reading the sys_ck rate directly. Signed-off-by: Paul Walmsley <paul@pwsan.com>
		
			
				
	
	
		
			246 lines
		
	
	
	
		
			6.1 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			246 lines
		
	
	
	
		
			6.1 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
/*
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 * OMAP2xxx DVFS virtual clock functions
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 *
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 * Copyright (C) 2005-2008 Texas Instruments, Inc.
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 * Copyright (C) 2004-2010 Nokia Corporation
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 *
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 * Contacts:
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 * Richard Woodruff <r-woodruff2@ti.com>
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 * Paul Walmsley
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 *
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 * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
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 * Gordon McNutt and RidgeRun, Inc.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License version 2 as
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 * published by the Free Software Foundation.
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 *
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 * XXX Some of this code should be replaceable by the upcoming OPP layer
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 * code.  However, some notion of "rate set" is probably still necessary
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 * for OMAP2xxx at least.  Rate sets should be generalized so they can be
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 * used for any OMAP chip, not just OMAP2xxx.  In particular, Richard Woodruff
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 * has in the past expressed a preference to use rate sets for OPP changes,
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 * rather than dynamically recalculating the clock tree, so if someone wants
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 * this badly enough to write the code to handle it, we should support it
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 * as an option.
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 */
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#undef DEBUG
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/cpufreq.h>
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#include <linux/slab.h>
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#include <plat/clock.h>
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#include <plat/sram.h>
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#include <plat/sdrc.h>
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#include "clock.h"
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#include "clock2xxx.h"
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#include "opp2xxx.h"
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#include "cm.h"
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#include "cm-regbits-24xx.h"
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const struct prcm_config *curr_prcm_set;
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const struct prcm_config *rate_table;
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/**
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 * omap2_table_mpu_recalc - just return the MPU speed
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 * @clk: virt_prcm_set struct clk
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 *
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 * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
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 */
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unsigned long omap2_table_mpu_recalc(struct clk *clk)
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{
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	return curr_prcm_set->mpu_speed;
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}
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/*
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 * Look for a rate equal or less than the target rate given a configuration set.
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 *
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 * What's not entirely clear is "which" field represents the key field.
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 * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
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 * just uses the ARM rates.
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 */
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long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
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{
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	const struct prcm_config *ptr;
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	long highest_rate;
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	highest_rate = -EINVAL;
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	for (ptr = rate_table; ptr->mpu_speed; ptr++) {
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		if (!(ptr->flags & cpu_mask))
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			continue;
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		if (ptr->xtal_speed != sclk->rate)
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			continue;
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		highest_rate = ptr->mpu_speed;
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		/* Can check only after xtal frequency check */
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		if (ptr->mpu_speed <= rate)
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			break;
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	}
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	return highest_rate;
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}
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/* Sets basic clocks based on the specified rate */
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int omap2_select_table_rate(struct clk *clk, unsigned long rate)
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{
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	u32 cur_rate, done_rate, bypass = 0, tmp;
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	const struct prcm_config *prcm;
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	unsigned long found_speed = 0;
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	unsigned long flags;
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	for (prcm = rate_table; prcm->mpu_speed; prcm++) {
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		if (!(prcm->flags & cpu_mask))
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			continue;
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		if (prcm->xtal_speed != sclk->rate)
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			continue;
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		if (prcm->mpu_speed <= rate) {
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			found_speed = prcm->mpu_speed;
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			break;
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		}
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	}
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	if (!found_speed) {
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		printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
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		       rate / 1000000);
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		return -EINVAL;
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	}
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	curr_prcm_set = prcm;
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	cur_rate = omap2xxx_clk_get_core_rate(dclk);
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	if (prcm->dpll_speed == cur_rate / 2) {
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		omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
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	} else if (prcm->dpll_speed == cur_rate * 2) {
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		omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
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	} else if (prcm->dpll_speed != cur_rate) {
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		local_irq_save(flags);
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		if (prcm->dpll_speed == prcm->xtal_speed)
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			bypass = 1;
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		if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
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		    CORE_CLK_SRC_DPLL_X2)
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			done_rate = CORE_CLK_SRC_DPLL_X2;
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		else
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			done_rate = CORE_CLK_SRC_DPLL;
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		/* MPU divider */
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		cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
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		/* dsp + iva1 div(2420), iva2.1(2430) */
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		cm_write_mod_reg(prcm->cm_clksel_dsp,
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				 OMAP24XX_DSP_MOD, CM_CLKSEL);
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		cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
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		/* Major subsystem dividers */
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		tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
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		cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
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				 CM_CLKSEL1);
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		if (cpu_is_omap2430())
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			cm_write_mod_reg(prcm->cm_clksel_mdm,
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					 OMAP2430_MDM_MOD, CM_CLKSEL);
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		/* x2 to enter omap2xxx_sdrc_init_params() */
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		omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
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		omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
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			       bypass);
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		omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
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		omap2xxx_sdrc_reprogram(done_rate, 0);
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		local_irq_restore(flags);
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	}
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	return 0;
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}
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#ifdef CONFIG_CPU_FREQ
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/*
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 * Walk PRCM rate table and fillout cpufreq freq_table
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 * XXX This should be replaced by an OPP layer in the near future
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 */
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static struct cpufreq_frequency_table *freq_table;
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void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
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{
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	const struct prcm_config *prcm;
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	int i = 0;
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	int tbl_sz = 0;
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	if (!cpu_is_omap24xx())
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		return;
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	for (prcm = rate_table; prcm->mpu_speed; prcm++) {
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		if (!(prcm->flags & cpu_mask))
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			continue;
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		if (prcm->xtal_speed != sclk->rate)
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			continue;
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		/* don't put bypass rates in table */
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		if (prcm->dpll_speed == prcm->xtal_speed)
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			continue;
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		tbl_sz++;
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	}
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	/*
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	 * XXX Ensure that we're doing what CPUFreq expects for this error
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	 * case and the following one
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	 */
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	if (tbl_sz == 0) {
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		pr_warning("%s: no matching entries in rate_table\n",
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			   __func__);
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		return;
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	}
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	/* Include the CPUFREQ_TABLE_END terminator entry */
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	tbl_sz++;
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	freq_table = kzalloc(sizeof(struct cpufreq_frequency_table) * tbl_sz,
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			     GFP_ATOMIC);
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	if (!freq_table) {
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		pr_err("%s: could not kzalloc frequency table\n", __func__);
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		return;
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	}
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	for (prcm = rate_table; prcm->mpu_speed; prcm++) {
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		if (!(prcm->flags & cpu_mask))
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			continue;
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		if (prcm->xtal_speed != sclk->rate)
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			continue;
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		/* don't put bypass rates in table */
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		if (prcm->dpll_speed == prcm->xtal_speed)
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			continue;
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		freq_table[i].index = i;
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		freq_table[i].frequency = prcm->mpu_speed / 1000;
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		i++;
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	}
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	freq_table[i].index = i;
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	freq_table[i].frequency = CPUFREQ_TABLE_END;
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	*table = &freq_table[0];
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}
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void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
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{
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	if (!cpu_is_omap24xx())
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		return;
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	kfree(freq_table);
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}
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#endif
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