51007004f4
In general we want to avoid ever touching memory while within an interrupt critical section, since the page fault path goes through a different path from the hypervisor when in an interrupt critical section, and we carefully decided with tilegx that we didn't need to support this path in the kernel. (On tilepro we did implement that path as part of supporting atomic instructions in software.) In practice we always need to touch the kernel stack, since that's where we store the interrupt state before releasing the critical section, but this change cleans up a few things. The IRQ_ENABLE macro is split up so that when we want to enable interrupts in a deferred way (e.g. for cpu_idle or for interrupt return) we can read the per-cpu enable mask before entering the critical section. The cache-migration code is changed to use interrupt masking instead of interrupt critical sections. And, the interrupt-entry code is changed so that we defer loading "tp" from per-cpu data until after we have released the interrupt critical section. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
192 lines
4 KiB
ArmAsm
192 lines
4 KiB
ArmAsm
/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*
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* This routine is a helper for migrating the home of a set of pages to
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* a new cpu. See the documentation in homecache.c for more information.
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*/
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#include <linux/linkage.h>
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#include <linux/threads.h>
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#include <asm/page.h>
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#include <asm/thread_info.h>
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#include <asm/types.h>
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#include <asm/asm-offsets.h>
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#include <hv/hypervisor.h>
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.text
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/*
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* First, some definitions that apply to all the code in the file.
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*/
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/* Locals (caller-save) */
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#define r_tmp r10
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#define r_save_sp r11
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/* What we save where in the stack frame; must include all callee-saves. */
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#define FRAME_SP 4
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#define FRAME_R30 8
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#define FRAME_R31 12
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#define FRAME_R32 16
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#define FRAME_R33 20
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#define FRAME_R34 24
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#define FRAME_SIZE 28
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/*
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* On entry:
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*
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* r0 low word of the new context PA to install (moved to r_context_lo)
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* r1 high word of the new context PA to install (moved to r_context_hi)
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* r2 low word of PTE to use for context access (moved to r_access_lo)
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* r3 high word of PTE to use for context access (moved to r_access_lo)
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* r4 ASID to use for new context (moved to r_asid)
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* r5 pointer to cpumask with just this cpu set in it (r_my_cpumask)
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*/
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/* Arguments (caller-save) */
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#define r_context_lo_in r0
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#define r_context_hi_in r1
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#define r_access_lo_in r2
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#define r_access_hi_in r3
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#define r_asid_in r4
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#define r_my_cpumask r5
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/* Locals (callee-save); must not be more than FRAME_xxx above. */
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#define r_context_lo r30
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#define r_context_hi r31
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#define r_access_lo r32
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#define r_access_hi r33
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#define r_asid r34
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STD_ENTRY(flush_and_install_context)
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/*
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* Create a stack frame; we can't touch it once we flush the
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* cache until we install the new page table and flush the TLB.
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*/
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{
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move r_save_sp, sp
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sw sp, lr
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addi sp, sp, -FRAME_SIZE
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}
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addi r_tmp, sp, FRAME_SP
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{
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sw r_tmp, r_save_sp
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addi r_tmp, sp, FRAME_R30
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}
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{
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sw r_tmp, r30
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addi r_tmp, sp, FRAME_R31
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}
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{
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sw r_tmp, r31
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addi r_tmp, sp, FRAME_R32
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}
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{
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sw r_tmp, r32
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addi r_tmp, sp, FRAME_R33
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}
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{
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sw r_tmp, r33
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addi r_tmp, sp, FRAME_R34
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}
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sw r_tmp, r34
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/* Move some arguments to callee-save registers. */
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{
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move r_context_lo, r_context_lo_in
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move r_context_hi, r_context_hi_in
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}
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{
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move r_access_lo, r_access_lo_in
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move r_access_hi, r_access_hi_in
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}
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move r_asid, r_asid_in
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/* First, flush our L2 cache. */
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{
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move r0, zero /* cache_pa */
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move r1, zero
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}
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{
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auli r2, zero, ha16(HV_FLUSH_EVICT_L2) /* cache_control */
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move r3, r_my_cpumask /* cache_cpumask */
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}
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{
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move r4, zero /* tlb_va */
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move r5, zero /* tlb_length */
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}
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{
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move r6, zero /* tlb_pgsize */
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move r7, zero /* tlb_cpumask */
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}
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{
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move r8, zero /* asids */
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move r9, zero /* asidcount */
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}
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jal hv_flush_remote
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bnz r0, .Ldone
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/* Now install the new page table. */
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{
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move r0, r_context_lo
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move r1, r_context_hi
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}
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{
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move r2, r_access_lo
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move r3, r_access_hi
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}
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{
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move r4, r_asid
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moveli r5, HV_CTX_DIRECTIO | CTX_PAGE_FLAG
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}
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jal hv_install_context
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bnz r0, .Ldone
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/* Finally, flush the TLB. */
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{
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movei r0, 0 /* preserve_global */
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jal hv_flush_all
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}
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.Ldone:
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/* Restore the callee-saved registers and return. */
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addli lr, sp, FRAME_SIZE
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{
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lw lr, lr
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addli r_tmp, sp, FRAME_R30
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}
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{
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lw r30, r_tmp
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addli r_tmp, sp, FRAME_R31
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}
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{
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lw r31, r_tmp
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addli r_tmp, sp, FRAME_R32
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}
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{
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lw r32, r_tmp
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addli r_tmp, sp, FRAME_R33
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}
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{
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lw r33, r_tmp
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addli r_tmp, sp, FRAME_R34
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}
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{
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lw r34, r_tmp
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addi sp, sp, FRAME_SIZE
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}
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jrp lr
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STD_ENDPROC(flush_and_install_context)
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