90563ec412
This patch adds the Dell Systems Management Base Driver with sysfs support. This driver has been tested with Dell OpenManage. Signed-off-by: Doug Warzecha <Douglas_Warzecha@dell.com> Cc: Greg KH <greg@kroah.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
107 lines
2.8 KiB
C
107 lines
2.8 KiB
C
/*
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* dcdbas.h: Definitions for Dell Systems Management Base driver
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*
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* Copyright (C) 1995-2005 Dell Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License v2.0 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _DCDBAS_H_
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#define _DCDBAS_H_
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#include <linux/device.h>
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#include <linux/input.h>
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#include <linux/sysfs.h>
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#include <linux/types.h>
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#define MAX_SMI_DATA_BUF_SIZE (256 * 1024)
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#define HC_ACTION_NONE (0)
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#define HC_ACTION_HOST_CONTROL_POWEROFF BIT(1)
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#define HC_ACTION_HOST_CONTROL_POWERCYCLE BIT(2)
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#define HC_SMITYPE_NONE (0)
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#define HC_SMITYPE_TYPE1 (1)
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#define HC_SMITYPE_TYPE2 (2)
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#define HC_SMITYPE_TYPE3 (3)
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#define ESM_APM_CMD (0x0A0)
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#define ESM_APM_POWER_CYCLE (0x10)
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#define ESM_STATUS_CMD_UNSUCCESSFUL (-1)
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#define CMOS_BASE_PORT (0x070)
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#define CMOS_PAGE1_INDEX_PORT (0)
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#define CMOS_PAGE1_DATA_PORT (1)
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#define CMOS_PAGE2_INDEX_PORT_PIIX4 (2)
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#define CMOS_PAGE2_DATA_PORT_PIIX4 (3)
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#define PE1400_APM_CONTROL_PORT (0x0B0)
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#define PCAT_APM_CONTROL_PORT (0x0B2)
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#define PCAT_APM_STATUS_PORT (0x0B3)
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#define PE1300_CMOS_CMD_STRUCT_PTR (0x38)
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#define PE1400_CMOS_CMD_STRUCT_PTR (0x70)
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#define MAX_SYSMGMT_SHORTCMD_PARMBUF_LEN (14)
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#define MAX_SYSMGMT_LONGCMD_SGENTRY_NUM (16)
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#define TIMEOUT_USEC_SHORT_SEMA_BLOCKING (10000)
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#define EXPIRED_TIMER (0)
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#define SMI_CMD_MAGIC (0x534D4931)
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#define DCDBAS_DEV_ATTR_RW(_name) \
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DEVICE_ATTR(_name,0600,_name##_show,_name##_store);
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#define DCDBAS_DEV_ATTR_RO(_name) \
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DEVICE_ATTR(_name,0400,_name##_show,NULL);
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#define DCDBAS_DEV_ATTR_WO(_name) \
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DEVICE_ATTR(_name,0200,NULL,_name##_store);
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#define DCDBAS_BIN_ATTR_RW(_name) \
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struct bin_attribute bin_attr_##_name = { \
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.attr = { .name = __stringify(_name), \
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.mode = 0600, \
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.owner = THIS_MODULE }, \
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.read = _name##_read, \
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.write = _name##_write, \
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}
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struct smi_cmd {
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__u32 magic;
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__u32 ebx;
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__u32 ecx;
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__u16 command_address;
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__u8 command_code;
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__u8 reserved;
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__u8 command_buffer[1];
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} __attribute__ ((packed));
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struct apm_cmd {
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__u8 command;
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__s8 status;
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__u16 reserved;
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union {
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struct {
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__u8 parm[MAX_SYSMGMT_SHORTCMD_PARMBUF_LEN];
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} __attribute__ ((packed)) shortreq;
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struct {
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__u16 num_sg_entries;
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struct {
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__u32 size;
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__u64 addr;
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} __attribute__ ((packed))
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sglist[MAX_SYSMGMT_LONGCMD_SGENTRY_NUM];
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} __attribute__ ((packed)) longreq;
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} __attribute__ ((packed)) parameters;
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} __attribute__ ((packed));
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#endif /* _DCDBAS_H_ */
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