9e13fbf7af
Move the drivers that use SEEQ chipset into drivers/net/ethernet/seeq and make the necessary Kconfig and Makefile changes. CC: Russell King <linux@arm.linux.org.uk> CC: Hamish Coleman <hamish@zot.apana.org.au> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
103 lines
4.5 KiB
C
103 lines
4.5 KiB
C
/*
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* sgiseeq.h: Defines for the Seeq8003 ethernet controller.
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*
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* Copyright (C) 1996 David S. Miller (davem@davemloft.net)
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*/
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#ifndef _SGISEEQ_H
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#define _SGISEEQ_H
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struct sgiseeq_wregs {
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volatile unsigned int multicase_high[2];
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volatile unsigned int frame_gap;
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volatile unsigned int control;
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};
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struct sgiseeq_rregs {
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volatile unsigned int collision_tx[2];
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volatile unsigned int collision_all[2];
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volatile unsigned int _unused0;
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volatile unsigned int rflags;
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};
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struct sgiseeq_regs {
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union {
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volatile unsigned int eth_addr[6];
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volatile unsigned int multicast_low[6];
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struct sgiseeq_wregs wregs;
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struct sgiseeq_rregs rregs;
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} rw;
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volatile unsigned int rstat;
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volatile unsigned int tstat;
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};
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/* Seeq8003 receive status register */
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#define SEEQ_RSTAT_OVERF 0x001 /* Overflow */
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#define SEEQ_RSTAT_CERROR 0x002 /* CRC error */
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#define SEEQ_RSTAT_DERROR 0x004 /* Dribble error */
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#define SEEQ_RSTAT_SFRAME 0x008 /* Short frame */
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#define SEEQ_RSTAT_REOF 0x010 /* Received end of frame */
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#define SEEQ_RSTAT_FIG 0x020 /* Frame is good */
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#define SEEQ_RSTAT_TIMEO 0x040 /* Timeout, or late receive */
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#define SEEQ_RSTAT_WHICH 0x080 /* Which status, 1=old 0=new */
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#define SEEQ_RSTAT_LITTLE 0x100 /* DMA is done in little endian format */
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#define SEEQ_RSTAT_SDMA 0x200 /* DMA has started */
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#define SEEQ_RSTAT_ADMA 0x400 /* DMA is active */
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#define SEEQ_RSTAT_ROVERF 0x800 /* Receive buffer overflow */
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/* Seeq8003 receive command register */
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#define SEEQ_RCMD_RDISAB 0x000 /* Disable receiver on the Seeq8003 */
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#define SEEQ_RCMD_IOVERF 0x001 /* IRQ on buffer overflows */
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#define SEEQ_RCMD_ICRC 0x002 /* IRQ on CRC errors */
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#define SEEQ_RCMD_IDRIB 0x004 /* IRQ on dribble errors */
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#define SEEQ_RCMD_ISHORT 0x008 /* IRQ on short frames */
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#define SEEQ_RCMD_IEOF 0x010 /* IRQ on end of frame */
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#define SEEQ_RCMD_IGOOD 0x020 /* IRQ on good frames */
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#define SEEQ_RCMD_RANY 0x040 /* Receive any frame */
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#define SEEQ_RCMD_RBCAST 0x080 /* Receive broadcasts */
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#define SEEQ_RCMD_RBMCAST 0x0c0 /* Receive broadcasts/multicasts */
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/* Seeq8003 transmit status register */
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#define SEEQ_TSTAT_UFLOW 0x001 /* Transmit buffer underflow */
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#define SEEQ_TSTAT_CLS 0x002 /* Collision detected */
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#define SEEQ_TSTAT_R16 0x004 /* Did 16 retries to tx a frame */
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#define SEEQ_TSTAT_PTRANS 0x008 /* Packet was transmitted ok */
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#define SEEQ_TSTAT_LCLS 0x010 /* Late collision occurred */
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#define SEEQ_TSTAT_WHICH 0x080 /* Which status, 1=old 0=new */
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#define SEEQ_TSTAT_TLE 0x100 /* DMA is done in little endian format */
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#define SEEQ_TSTAT_SDMA 0x200 /* DMA has started */
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#define SEEQ_TSTAT_ADMA 0x400 /* DMA is active */
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/* Seeq8003 transmit command register */
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#define SEEQ_TCMD_RB0 0x00 /* Register bank zero w/station addr */
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#define SEEQ_TCMD_IUF 0x01 /* IRQ on tx underflow */
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#define SEEQ_TCMD_IC 0x02 /* IRQ on collisions */
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#define SEEQ_TCMD_I16 0x04 /* IRQ after 16 failed attempts to tx frame */
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#define SEEQ_TCMD_IPT 0x08 /* IRQ when packet successfully transmitted */
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#define SEEQ_TCMD_RB1 0x20 /* Register bank one w/multi-cast low byte */
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#define SEEQ_TCMD_RB2 0x40 /* Register bank two w/multi-cast high byte */
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/* Seeq8003 control register */
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#define SEEQ_CTRL_XCNT 0x01
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#define SEEQ_CTRL_ACCNT 0x02
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#define SEEQ_CTRL_SFLAG 0x04
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#define SEEQ_CTRL_EMULTI 0x08
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#define SEEQ_CTRL_ESHORT 0x10
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#define SEEQ_CTRL_ENCARR 0x20
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/* Seeq8003 control registers on the SGI Hollywood HPC. */
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#define SEEQ_HPIO_P1BITS 0x00000001 /* cycles to stay in P1 phase for PIO */
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#define SEEQ_HPIO_P2BITS 0x00000060 /* cycles to stay in P2 phase for PIO */
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#define SEEQ_HPIO_P3BITS 0x00000100 /* cycles to stay in P3 phase for PIO */
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#define SEEQ_HDMA_D1BITS 0x00000006 /* cycles to stay in D1 phase for DMA */
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#define SEEQ_HDMA_D2BITS 0x00000020 /* cycles to stay in D2 phase for DMA */
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#define SEEQ_HDMA_D3BITS 0x00000000 /* cycles to stay in D3 phase for DMA */
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#define SEEQ_HDMA_TIMEO 0x00030000 /* cycles for DMA timeout */
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#define SEEQ_HCTL_NORM 0x00000000 /* Normal operation mode */
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#define SEEQ_HCTL_RESET 0x00000001 /* Reset Seeq8003 and HPC interface */
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#define SEEQ_HCTL_IPEND 0x00000002 /* IRQ is pending for the chip */
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#define SEEQ_HCTL_IPG 0x00001000 /* Inter-packet gap */
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#define SEEQ_HCTL_RFIX 0x00002000 /* At rxdc, clear end-of-packet */
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#define SEEQ_HCTL_EFIX 0x00004000 /* fixes intr status bit settings */
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#define SEEQ_HCTL_IFIX 0x00008000 /* enable startup timeouts */
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#endif /* !(_SGISEEQ_H) */
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