2048e3286f
This patch adds the basic structure of a DRM Driver for Rockchip Socs. Signed-off-by: Mark Yao <mark.yao@rock-chips.com> Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Acked-by: Daniel Vetter <daniel@ffwll.ch> Reviewed-by: Rob Clark <robdclark@gmail.com>
201 lines
5.7 KiB
C
201 lines
5.7 KiB
C
/*
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* Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
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* Author:Mark Yao <mark.yao@rock-chips.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _ROCKCHIP_DRM_VOP_H
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#define _ROCKCHIP_DRM_VOP_H
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/* register definition */
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#define REG_CFG_DONE 0x0000
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#define VERSION_INFO 0x0004
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#define SYS_CTRL 0x0008
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#define SYS_CTRL1 0x000c
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#define DSP_CTRL0 0x0010
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#define DSP_CTRL1 0x0014
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#define DSP_BG 0x0018
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#define MCU_CTRL 0x001c
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#define INTR_CTRL0 0x0020
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#define INTR_CTRL1 0x0024
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#define WIN0_CTRL0 0x0030
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#define WIN0_CTRL1 0x0034
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#define WIN0_COLOR_KEY 0x0038
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#define WIN0_VIR 0x003c
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#define WIN0_YRGB_MST 0x0040
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#define WIN0_CBR_MST 0x0044
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#define WIN0_ACT_INFO 0x0048
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#define WIN0_DSP_INFO 0x004c
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#define WIN0_DSP_ST 0x0050
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#define WIN0_SCL_FACTOR_YRGB 0x0054
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#define WIN0_SCL_FACTOR_CBR 0x0058
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#define WIN0_SCL_OFFSET 0x005c
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#define WIN0_SRC_ALPHA_CTRL 0x0060
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#define WIN0_DST_ALPHA_CTRL 0x0064
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#define WIN0_FADING_CTRL 0x0068
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/* win1 register */
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#define WIN1_CTRL0 0x0070
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#define WIN1_CTRL1 0x0074
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#define WIN1_COLOR_KEY 0x0078
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#define WIN1_VIR 0x007c
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#define WIN1_YRGB_MST 0x0080
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#define WIN1_CBR_MST 0x0084
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#define WIN1_ACT_INFO 0x0088
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#define WIN1_DSP_INFO 0x008c
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#define WIN1_DSP_ST 0x0090
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#define WIN1_SCL_FACTOR_YRGB 0x0094
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#define WIN1_SCL_FACTOR_CBR 0x0098
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#define WIN1_SCL_OFFSET 0x009c
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#define WIN1_SRC_ALPHA_CTRL 0x00a0
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#define WIN1_DST_ALPHA_CTRL 0x00a4
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#define WIN1_FADING_CTRL 0x00a8
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/* win2 register */
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#define WIN2_CTRL0 0x00b0
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#define WIN2_CTRL1 0x00b4
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#define WIN2_VIR0_1 0x00b8
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#define WIN2_VIR2_3 0x00bc
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#define WIN2_MST0 0x00c0
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#define WIN2_DSP_INFO0 0x00c4
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#define WIN2_DSP_ST0 0x00c8
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#define WIN2_COLOR_KEY 0x00cc
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#define WIN2_MST1 0x00d0
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#define WIN2_DSP_INFO1 0x00d4
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#define WIN2_DSP_ST1 0x00d8
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#define WIN2_SRC_ALPHA_CTRL 0x00dc
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#define WIN2_MST2 0x00e0
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#define WIN2_DSP_INFO2 0x00e4
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#define WIN2_DSP_ST2 0x00e8
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#define WIN2_DST_ALPHA_CTRL 0x00ec
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#define WIN2_MST3 0x00f0
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#define WIN2_DSP_INFO3 0x00f4
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#define WIN2_DSP_ST3 0x00f8
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#define WIN2_FADING_CTRL 0x00fc
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/* win3 register */
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#define WIN3_CTRL0 0x0100
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#define WIN3_CTRL1 0x0104
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#define WIN3_VIR0_1 0x0108
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#define WIN3_VIR2_3 0x010c
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#define WIN3_MST0 0x0110
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#define WIN3_DSP_INFO0 0x0114
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#define WIN3_DSP_ST0 0x0118
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#define WIN3_COLOR_KEY 0x011c
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#define WIN3_MST1 0x0120
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#define WIN3_DSP_INFO1 0x0124
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#define WIN3_DSP_ST1 0x0128
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#define WIN3_SRC_ALPHA_CTRL 0x012c
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#define WIN3_MST2 0x0130
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#define WIN3_DSP_INFO2 0x0134
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#define WIN3_DSP_ST2 0x0138
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#define WIN3_DST_ALPHA_CTRL 0x013c
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#define WIN3_MST3 0x0140
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#define WIN3_DSP_INFO3 0x0144
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#define WIN3_DSP_ST3 0x0148
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#define WIN3_FADING_CTRL 0x014c
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/* hwc register */
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#define HWC_CTRL0 0x0150
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#define HWC_CTRL1 0x0154
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#define HWC_MST 0x0158
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#define HWC_DSP_ST 0x015c
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#define HWC_SRC_ALPHA_CTRL 0x0160
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#define HWC_DST_ALPHA_CTRL 0x0164
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#define HWC_FADING_CTRL 0x0168
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/* post process register */
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#define POST_DSP_HACT_INFO 0x0170
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#define POST_DSP_VACT_INFO 0x0174
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#define POST_SCL_FACTOR_YRGB 0x0178
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#define POST_SCL_CTRL 0x0180
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#define POST_DSP_VACT_INFO_F1 0x0184
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#define DSP_HTOTAL_HS_END 0x0188
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#define DSP_HACT_ST_END 0x018c
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#define DSP_VTOTAL_VS_END 0x0190
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#define DSP_VACT_ST_END 0x0194
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#define DSP_VS_ST_END_F1 0x0198
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#define DSP_VACT_ST_END_F1 0x019c
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/* register definition end */
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/* interrupt define */
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#define DSP_HOLD_VALID_INTR (1 << 0)
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#define FS_INTR (1 << 1)
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#define LINE_FLAG_INTR (1 << 2)
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#define BUS_ERROR_INTR (1 << 3)
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#define INTR_MASK (DSP_HOLD_VALID_INTR | FS_INTR | \
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LINE_FLAG_INTR | BUS_ERROR_INTR)
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#define DSP_HOLD_VALID_INTR_EN(x) ((x) << 4)
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#define FS_INTR_EN(x) ((x) << 5)
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#define LINE_FLAG_INTR_EN(x) ((x) << 6)
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#define BUS_ERROR_INTR_EN(x) ((x) << 7)
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#define DSP_HOLD_VALID_INTR_MASK (1 << 4)
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#define FS_INTR_MASK (1 << 5)
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#define LINE_FLAG_INTR_MASK (1 << 6)
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#define BUS_ERROR_INTR_MASK (1 << 7)
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#define INTR_CLR_SHIFT 8
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#define DSP_HOLD_VALID_INTR_CLR (1 << (INTR_CLR_SHIFT + 0))
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#define FS_INTR_CLR (1 << (INTR_CLR_SHIFT + 1))
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#define LINE_FLAG_INTR_CLR (1 << (INTR_CLR_SHIFT + 2))
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#define BUS_ERROR_INTR_CLR (1 << (INTR_CLR_SHIFT + 3))
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#define DSP_LINE_NUM(x) (((x) & 0x1fff) << 12)
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#define DSP_LINE_NUM_MASK (0x1fff << 12)
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/* src alpha ctrl define */
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#define SRC_FADING_VALUE(x) (((x) & 0xff) << 24)
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#define SRC_GLOBAL_ALPHA(x) (((x) & 0xff) << 16)
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#define SRC_FACTOR_M0(x) (((x) & 0x7) << 6)
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#define SRC_ALPHA_CAL_M0(x) (((x) & 0x1) << 5)
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#define SRC_BLEND_M0(x) (((x) & 0x3) << 3)
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#define SRC_ALPHA_M0(x) (((x) & 0x1) << 2)
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#define SRC_COLOR_M0(x) (((x) & 0x1) << 1)
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#define SRC_ALPHA_EN(x) (((x) & 0x1) << 0)
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/* dst alpha ctrl define */
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#define DST_FACTOR_M0(x) (((x) & 0x7) << 6)
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/*
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* display output interface supported by rockchip lcdc
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*/
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#define ROCKCHIP_OUT_MODE_P888 0
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#define ROCKCHIP_OUT_MODE_P666 1
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#define ROCKCHIP_OUT_MODE_P565 2
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/* for use special outface */
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#define ROCKCHIP_OUT_MODE_AAAA 15
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enum alpha_mode {
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ALPHA_STRAIGHT,
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ALPHA_INVERSE,
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};
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enum global_blend_mode {
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ALPHA_GLOBAL,
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ALPHA_PER_PIX,
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ALPHA_PER_PIX_GLOBAL,
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};
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enum alpha_cal_mode {
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ALPHA_SATURATION,
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ALPHA_NO_SATURATION,
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};
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enum color_mode {
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ALPHA_SRC_PRE_MUL,
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ALPHA_SRC_NO_PRE_MUL,
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};
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enum factor_mode {
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ALPHA_ZERO,
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ALPHA_ONE,
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ALPHA_SRC,
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ALPHA_SRC_INVERSE,
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ALPHA_SRC_GLOBAL,
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};
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#endif /* _ROCKCHIP_DRM_VOP_H */
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