- armada 370/375
     - Fix SSCG node lookup
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2
 
 iQIcBAABAgAGBQJULVYpAAoJEP45WPkGe8ZnSOAP/2V3KoDeaINR0cGG/u/YI/hp
 M5E4nZtRF9rZS3WMhULVjevcoddClDpvSJIvW34ZEI5uWc+kqkq+Q5Jj23t1oczq
 f5TqRDR2GenvxF1RbNGazZhLUJE6ubV1ADRKZNdRYfwR33RgrjRmWe2xrQ4vpemf
 58BSYbYwsrySd6s7KRJaSnSLrhxywPZCaisod4oquZF75cZ3W63V9RugHGADu/SZ
 gSxU+0bN4nbU8MFQxyaKq94FeyaAoDPkrMiSXAtjPQzl9a4zZd+BD/KArnf5LCs/
 kmRUfOQ38p4KIH9W49YRESZdh2/jUO+3hFTSsAKcXid7ZTadSH/WKHC4LCXH5Td6
 ST1fq0gGTPwDqULSCguw0n/UgIsn3D3fI3ruXuAAoV1S36Hzsh6n3dhZunfE9V/Y
 yKjf36GHT6g9a3CV3CEuSY18mLdDvkN9F/4A2mGhVHt11gl0JbaAKPb0D1GWzucP
 1N24NqCZ8/tOO4J3wseqvEW0imsZY4GB5CauJr9bgARaZhv2rjks79KExgpoTyk3
 ttDMl2JAspcZntHQQxVBGa3buux11SAH4jUdhtJC8BNGFXPo9XThNS2m+shseSJP
 UDlo6SWSMNohwAcWVSyEGkTHSe7Z2h3+PHDBKB8LwW8he9EIbCsxKJgk+Uz/gq8x
 8uMlUwJz1LajKur3+MSP
 =q4nx
 -----END PGP SIGNATURE-----
Merge tag 'clk-mvebu-3.18-2' of git://git.infradead.org/linux-mvebu into clk-next
clock mvebu changes for v3.18 (round 2)
 - armada 370/375
    - Fix SSCG node lookup
		
	
			
		
			
				
	
	
		
			57 lines
		
	
	
	
		
			1.4 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			57 lines
		
	
	
	
		
			1.4 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
/*
 | 
						|
 * Marvell EBU SoC common clock handling
 | 
						|
 *
 | 
						|
 * Copyright (C) 2012 Marvell
 | 
						|
 *
 | 
						|
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 | 
						|
 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
 | 
						|
 * Andrew Lunn <andrew@lunn.ch>
 | 
						|
 *
 | 
						|
 * This file is licensed under the terms of the GNU General Public
 | 
						|
 * License version 2. This program is licensed "as is" without any
 | 
						|
 * warranty of any kind, whether express or implied.
 | 
						|
 */
 | 
						|
 | 
						|
#ifndef __CLK_MVEBU_COMMON_H_
 | 
						|
#define __CLK_MVEBU_COMMON_H_
 | 
						|
 | 
						|
#include <linux/kernel.h>
 | 
						|
 | 
						|
extern spinlock_t ctrl_gating_lock;
 | 
						|
 | 
						|
struct device_node;
 | 
						|
 | 
						|
struct coreclk_ratio {
 | 
						|
	int id;
 | 
						|
	const char *name;
 | 
						|
};
 | 
						|
 | 
						|
struct coreclk_soc_desc {
 | 
						|
	u32 (*get_tclk_freq)(void __iomem *sar);
 | 
						|
	u32 (*get_cpu_freq)(void __iomem *sar);
 | 
						|
	void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div);
 | 
						|
	bool (*is_sscg_enabled)(void __iomem *sar);
 | 
						|
	u32 (*fix_sscg_deviation)(u32 system_clk);
 | 
						|
	const struct coreclk_ratio *ratios;
 | 
						|
	int num_ratios;
 | 
						|
};
 | 
						|
 | 
						|
struct clk_gating_soc_desc {
 | 
						|
	const char *name;
 | 
						|
	const char *parent;
 | 
						|
	int bit_idx;
 | 
						|
	unsigned long flags;
 | 
						|
};
 | 
						|
 | 
						|
void __init mvebu_coreclk_setup(struct device_node *np,
 | 
						|
				const struct coreclk_soc_desc *desc);
 | 
						|
 | 
						|
void __init mvebu_clk_gating_setup(struct device_node *np,
 | 
						|
				   const struct clk_gating_soc_desc *desc);
 | 
						|
 | 
						|
/*
 | 
						|
 * This function is shared among the Kirkwood, Armada 370, Armada XP
 | 
						|
 * and Armada 375 SoC
 | 
						|
 */
 | 
						|
u32 kirkwood_fix_sscg_deviation(u32 system_clk);
 | 
						|
#endif
 |