72c5839515
GICv3 introduces new system registers accessible with the full msr/mrs syntax (e.g. mrs x0, Sop0_op1_CRm_CRn_op2). However, only recent binutils understand the new syntax. This patch introduces msr_s/mrs_s assembly macros which generate the equivalent instructions above and converts the existing GICv3 code (both drivers/irqchip/ and arch/arm64/kernel/). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Reported-by: Olof Johansson <olof@lixom.net> Tested-by: Olof Johansson <olof@lixom.net> Suggested-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Jason Cooper <jason@lakedaemon.net> Cc: Will Deacon <will.deacon@arm.com> Cc: Marc Zyngier <marc.zyngier@arm.com>
60 lines
1.6 KiB
C
60 lines
1.6 KiB
C
/*
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* Macros for accessing system registers with older binutils.
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*
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* Copyright (C) 2014 ARM Ltd.
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* Author: Catalin Marinas <catalin.marinas@arm.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_SYSREG_H
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#define __ASM_SYSREG_H
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#define sys_reg(op0, op1, crn, crm, op2) \
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((((op0)-2)<<19)|((op1)<<16)|((crn)<<12)|((crm)<<8)|((op2)<<5))
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#ifdef __ASSEMBLY__
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.irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
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.equ __reg_num_x\num, \num
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.endr
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.equ __reg_num_xzr, 31
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.macro mrs_s, rt, sreg
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.inst 0xd5300000|(\sreg)|(__reg_num_\rt)
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.endm
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.macro msr_s, sreg, rt
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.inst 0xd5100000|(\sreg)|(__reg_num_\rt)
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.endm
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#else
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asm(
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" .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n"
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" .equ __reg_num_x\\num, \\num\n"
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" .endr\n"
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" .equ __reg_num_xzr, 31\n"
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"\n"
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" .macro mrs_s, rt, sreg\n"
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" .inst 0xd5300000|(\\sreg)|(__reg_num_\\rt)\n"
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" .endm\n"
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"\n"
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" .macro msr_s, sreg, rt\n"
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" .inst 0xd5100000|(\\sreg)|(__reg_num_\\rt)\n"
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" .endm\n"
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);
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#endif
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#endif /* __ASM_SYSREG_H */
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