 7acf71d1a2
			
		
	
	
	7acf71d1a2
	
	
	
		
			
			Some of the KGDB macros used for generating the BRK instructions had the wrong spelling for DBG and KGDB abbreviations. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
		
			
				
	
	
		
			158 lines
		
	
	
	
		
			4.2 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			158 lines
		
	
	
	
		
			4.2 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * Copyright (C) 2012 ARM Ltd.
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|  *
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|  * This program is free software; you can redistribute it and/or modify
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|  * it under the terms of the GNU General Public License version 2 as
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|  * published by the Free Software Foundation.
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|  *
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|  * This program is distributed in the hope that it will be useful,
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|  * but WITHOUT ANY WARRANTY; without even the implied warranty of
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|  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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|  * GNU General Public License for more details.
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|  *
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|  * You should have received a copy of the GNU General Public License
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|  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
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|  */
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| #ifndef __ASM_DEBUG_MONITORS_H
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| #define __ASM_DEBUG_MONITORS_H
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| 
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| #ifdef __KERNEL__
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| 
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| /* Low-level stepping controls. */
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| #define DBG_MDSCR_SS		(1 << 0)
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| #define DBG_SPSR_SS		(1 << 21)
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| 
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| /* MDSCR_EL1 enabling bits */
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| #define DBG_MDSCR_KDE		(1 << 13)
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| #define DBG_MDSCR_MDE		(1 << 15)
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| #define DBG_MDSCR_MASK		~(DBG_MDSCR_KDE | DBG_MDSCR_MDE)
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| 
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| #define	DBG_ESR_EVT(x)		(((x) >> 27) & 0x7)
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| 
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| /* AArch64 */
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| #define DBG_ESR_EVT_HWBP	0x0
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| #define DBG_ESR_EVT_HWSS	0x1
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| #define DBG_ESR_EVT_HWWP	0x2
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| #define DBG_ESR_EVT_BRK		0x6
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| 
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| /*
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|  * Break point instruction encoding
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|  */
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| #define BREAK_INSTR_SIZE		4
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| 
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| /*
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|  * ESR values expected for dynamic and compile time BRK instruction
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|  */
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| #define DBG_ESR_VAL_BRK(x)	(0xf2000000 | ((x) & 0xfffff))
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| 
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| /*
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|  * #imm16 values used for BRK instruction generation
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|  * Allowed values for kgbd are 0x400 - 0x7ff
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|  * 0x100: for triggering a fault on purpose (reserved)
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|  * 0x400: for dynamic BRK instruction
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|  * 0x401: for compile time BRK instruction
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|  */
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| #define FAULT_BRK_IMM			0x100
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| #define KGDB_DYN_DBG_BRK_IMM		0x400
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| #define KGDB_COMPILED_DBG_BRK_IMM	0x401
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| 
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| /*
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|  * BRK instruction encoding
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|  * The #imm16 value should be placed at bits[20:5] within BRK ins
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|  */
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| #define AARCH64_BREAK_MON	0xd4200000
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| 
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| /*
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|  * BRK instruction for provoking a fault on purpose
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|  * Unlike kgdb, #imm16 value with unallocated handler is used for faulting.
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|  */
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| #define AARCH64_BREAK_FAULT	(AARCH64_BREAK_MON | (FAULT_BRK_IMM << 5))
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| 
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| /*
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|  * Extract byte from BRK instruction
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|  */
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| #define KGDB_DYN_DBG_BRK_INS_BYTE(x) \
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| 	((((AARCH64_BREAK_MON) & 0xffe0001f) >> (x * 8)) & 0xff)
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| 
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| /*
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|  * Extract byte from BRK #imm16
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|  */
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| #define KGBD_DYN_DBG_BRK_IMM_BYTE(x) \
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| 	(((((KGDB_DYN_DBG_BRK_IMM) & 0xffff) << 5) >> (x * 8)) & 0xff)
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| 
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| #define KGDB_DYN_DBG_BRK_BYTE(x) \
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| 	(KGDB_DYN_DBG_BRK_INS_BYTE(x) | KGBD_DYN_DBG_BRK_IMM_BYTE(x))
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| 
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| #define  KGDB_DYN_BRK_INS_BYTE0  KGDB_DYN_DBG_BRK_BYTE(0)
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| #define  KGDB_DYN_BRK_INS_BYTE1  KGDB_DYN_DBG_BRK_BYTE(1)
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| #define  KGDB_DYN_BRK_INS_BYTE2  KGDB_DYN_DBG_BRK_BYTE(2)
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| #define  KGDB_DYN_BRK_INS_BYTE3  KGDB_DYN_DBG_BRK_BYTE(3)
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| 
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| #define CACHE_FLUSH_IS_SAFE		1
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| 
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| /* AArch32 */
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| #define DBG_ESR_EVT_BKPT	0x4
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| #define DBG_ESR_EVT_VECC	0x5
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| 
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| #define AARCH32_BREAK_ARM	0x07f001f0
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| #define AARCH32_BREAK_THUMB	0xde01
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| #define AARCH32_BREAK_THUMB2_LO	0xf7f0
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| #define AARCH32_BREAK_THUMB2_HI	0xa000
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| 
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| #ifndef __ASSEMBLY__
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| struct task_struct;
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| 
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| #define DBG_ARCH_ID_RESERVED	0	/* In case of ptrace ABI updates. */
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| 
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| #define DBG_HOOK_HANDLED	0
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| #define DBG_HOOK_ERROR		1
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| 
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| struct step_hook {
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| 	struct list_head node;
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| 	int (*fn)(struct pt_regs *regs, unsigned int esr);
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| };
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| 
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| void register_step_hook(struct step_hook *hook);
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| void unregister_step_hook(struct step_hook *hook);
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| 
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| struct break_hook {
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| 	struct list_head node;
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| 	u32 esr_val;
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| 	u32 esr_mask;
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| 	int (*fn)(struct pt_regs *regs, unsigned int esr);
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| };
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| 
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| void register_break_hook(struct break_hook *hook);
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| void unregister_break_hook(struct break_hook *hook);
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| 
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| u8 debug_monitors_arch(void);
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| 
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| enum debug_el {
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| 	DBG_ACTIVE_EL0 = 0,
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| 	DBG_ACTIVE_EL1,
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| };
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| 
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| void enable_debug_monitors(enum debug_el el);
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| void disable_debug_monitors(enum debug_el el);
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| 
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| void user_rewind_single_step(struct task_struct *task);
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| void user_fastforward_single_step(struct task_struct *task);
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| 
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| void kernel_enable_single_step(struct pt_regs *regs);
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| void kernel_disable_single_step(void);
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| int kernel_active_single_step(void);
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| 
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| #ifdef CONFIG_HAVE_HW_BREAKPOINT
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| int reinstall_suspended_bps(struct pt_regs *regs);
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| #else
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| static inline int reinstall_suspended_bps(struct pt_regs *regs)
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| {
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| 	return -ENODEV;
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| }
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| #endif
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| 
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| int aarch32_break_handler(struct pt_regs *regs);
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| 
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| #endif	/* __ASSEMBLY */
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| #endif	/* __KERNEL__ */
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| #endif	/* __ASM_DEBUG_MONITORS_H */
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