e9dff0ee66
Mark i386-specific cpu cache functions as __cpuinit. They are all only called from arch/i386/common.c:display_cache_info() that already is marked as __cpuinit. Signed-off-by: Magnus Damm <magnus@valinux.co.jp> Signed-off-by: Andi Kleen <ak@suse.de>
295 lines
7.4 KiB
C
295 lines
7.4 KiB
C
#include <linux/init.h>
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#include <linux/bitops.h>
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#include <linux/mm.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include "cpu.h"
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/*
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* B step AMD K6 before B 9730xxxx have hardware bugs that can cause
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* misexecution of code under Linux. Owners of such processors should
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* contact AMD for precise details and a CPU swap.
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*
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* See http://www.multimania.com/poulot/k6bug.html
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* http://www.amd.com/K6/k6docs/revgd.html
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*
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* The following test is erm.. interesting. AMD neglected to up
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* the chip setting when fixing the bug but they also tweaked some
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* performance at the same time..
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*/
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extern void vide(void);
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__asm__(".align 4\nvide: ret");
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static void __cpuinit init_amd(struct cpuinfo_x86 *c)
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{
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u32 l, h;
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int mbytes = num_physpages >> (20-PAGE_SHIFT);
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int r;
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#ifdef CONFIG_SMP
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unsigned long long value;
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/* Disable TLB flush filter by setting HWCR.FFDIS on K8
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* bit 6 of msr C001_0015
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*
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* Errata 63 for SH-B3 steppings
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* Errata 122 for all steppings (F+ have it disabled by default)
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*/
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if (c->x86 == 15) {
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rdmsrl(MSR_K7_HWCR, value);
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value |= 1 << 6;
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wrmsrl(MSR_K7_HWCR, value);
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}
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#endif
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/*
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* FIXME: We should handle the K5 here. Set up the write
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* range and also turn on MSR 83 bits 4 and 31 (write alloc,
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* no bus pipeline)
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*/
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/* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
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3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
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clear_bit(0*32+31, c->x86_capability);
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r = get_model_name(c);
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switch(c->x86)
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{
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case 4:
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/*
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* General Systems BIOSen alias the cpu frequency registers
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* of the Elan at 0x000df000. Unfortuantly, one of the Linux
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* drivers subsequently pokes it, and changes the CPU speed.
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* Workaround : Remove the unneeded alias.
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*/
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#define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
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#define CBAR_ENB (0x80000000)
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#define CBAR_KEY (0X000000CB)
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if (c->x86_model==9 || c->x86_model == 10) {
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if (inl (CBAR) & CBAR_ENB)
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outl (0 | CBAR_KEY, CBAR);
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}
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break;
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case 5:
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if( c->x86_model < 6 )
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{
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/* Based on AMD doc 20734R - June 2000 */
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if ( c->x86_model == 0 ) {
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clear_bit(X86_FEATURE_APIC, c->x86_capability);
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set_bit(X86_FEATURE_PGE, c->x86_capability);
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}
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break;
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}
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if ( c->x86_model == 6 && c->x86_mask == 1 ) {
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const int K6_BUG_LOOP = 1000000;
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int n;
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void (*f_vide)(void);
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unsigned long d, d2;
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printk(KERN_INFO "AMD K6 stepping B detected - ");
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/*
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* It looks like AMD fixed the 2.6.2 bug and improved indirect
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* calls at the same time.
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*/
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n = K6_BUG_LOOP;
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f_vide = vide;
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rdtscl(d);
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while (n--)
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f_vide();
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rdtscl(d2);
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d = d2-d;
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/* Knock these two lines out if it debugs out ok */
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printk(KERN_INFO "AMD K6 stepping B detected - ");
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/* -- cut here -- */
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if (d > 20*K6_BUG_LOOP)
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printk("system stability may be impaired when more than 32 MB are used.\n");
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else
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printk("probably OK (after B9730xxxx).\n");
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printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
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}
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/* K6 with old style WHCR */
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if (c->x86_model < 8 ||
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(c->x86_model== 8 && c->x86_mask < 8)) {
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/* We can only write allocate on the low 508Mb */
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if(mbytes>508)
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mbytes=508;
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rdmsr(MSR_K6_WHCR, l, h);
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if ((l&0x0000FFFF)==0) {
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unsigned long flags;
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l=(1<<0)|((mbytes/4)<<1);
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local_irq_save(flags);
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wbinvd();
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wrmsr(MSR_K6_WHCR, l, h);
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local_irq_restore(flags);
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printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
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mbytes);
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}
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break;
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}
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if ((c->x86_model == 8 && c->x86_mask >7) ||
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c->x86_model == 9 || c->x86_model == 13) {
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/* The more serious chips .. */
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if(mbytes>4092)
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mbytes=4092;
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rdmsr(MSR_K6_WHCR, l, h);
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if ((l&0xFFFF0000)==0) {
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unsigned long flags;
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l=((mbytes>>2)<<22)|(1<<16);
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local_irq_save(flags);
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wbinvd();
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wrmsr(MSR_K6_WHCR, l, h);
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local_irq_restore(flags);
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printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
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mbytes);
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}
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/* Set MTRR capability flag if appropriate */
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if (c->x86_model == 13 || c->x86_model == 9 ||
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(c->x86_model == 8 && c->x86_mask >= 8))
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set_bit(X86_FEATURE_K6_MTRR, c->x86_capability);
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break;
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}
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if (c->x86_model == 10) {
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/* AMD Geode LX is model 10 */
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/* placeholder for any needed mods */
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break;
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}
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break;
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case 6: /* An Athlon/Duron */
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/* Bit 15 of Athlon specific MSR 15, needs to be 0
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* to enable SSE on Palomino/Morgan/Barton CPU's.
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* If the BIOS didn't enable it already, enable it here.
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*/
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if (c->x86_model >= 6 && c->x86_model <= 10) {
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if (!cpu_has(c, X86_FEATURE_XMM)) {
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printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
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rdmsr(MSR_K7_HWCR, l, h);
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l &= ~0x00008000;
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wrmsr(MSR_K7_HWCR, l, h);
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set_bit(X86_FEATURE_XMM, c->x86_capability);
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}
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}
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/* It's been determined by AMD that Athlons since model 8 stepping 1
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* are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
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* As per AMD technical note 27212 0.2
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*/
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if ((c->x86_model == 8 && c->x86_mask>=1) || (c->x86_model > 8)) {
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rdmsr(MSR_K7_CLK_CTL, l, h);
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if ((l & 0xfff00000) != 0x20000000) {
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printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l,
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((l & 0x000fffff)|0x20000000));
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wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
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}
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}
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break;
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}
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switch (c->x86) {
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case 15:
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set_bit(X86_FEATURE_K8, c->x86_capability);
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break;
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case 6:
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set_bit(X86_FEATURE_K7, c->x86_capability);
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break;
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}
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if (c->x86 >= 6)
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set_bit(X86_FEATURE_FXSAVE_LEAK, c->x86_capability);
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display_cacheinfo(c);
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if (cpuid_eax(0x80000000) >= 0x80000008) {
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c->x86_max_cores = (cpuid_ecx(0x80000008) & 0xff) + 1;
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}
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if (cpuid_eax(0x80000000) >= 0x80000007) {
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c->x86_power = cpuid_edx(0x80000007);
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if (c->x86_power & (1<<8))
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set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
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}
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#ifdef CONFIG_X86_HT
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/*
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* On a AMD multi core setup the lower bits of the APIC id
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* distingush the cores.
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*/
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if (c->x86_max_cores > 1) {
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int cpu = smp_processor_id();
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unsigned bits = (cpuid_ecx(0x80000008) >> 12) & 0xf;
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if (bits == 0) {
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while ((1 << bits) < c->x86_max_cores)
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bits++;
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}
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c->cpu_core_id = c->phys_proc_id & ((1<<bits)-1);
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c->phys_proc_id >>= bits;
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printk(KERN_INFO "CPU %d(%d) -> Core %d\n",
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cpu, c->x86_max_cores, c->cpu_core_id);
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}
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#endif
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if (cpuid_eax(0x80000000) >= 0x80000006)
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num_cache_leaves = 3;
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}
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static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 * c, unsigned int size)
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{
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/* AMD errata T13 (order #21922) */
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if ((c->x86 == 6)) {
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if (c->x86_model == 3 && c->x86_mask == 0) /* Duron Rev A0 */
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size = 64;
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if (c->x86_model == 4 &&
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(c->x86_mask==0 || c->x86_mask==1)) /* Tbird rev A1/A2 */
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size = 256;
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}
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return size;
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}
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static struct cpu_dev amd_cpu_dev __cpuinitdata = {
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.c_vendor = "AMD",
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.c_ident = { "AuthenticAMD" },
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.c_models = {
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{ .vendor = X86_VENDOR_AMD, .family = 4, .model_names =
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{
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[3] = "486 DX/2",
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[7] = "486 DX/2-WB",
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[8] = "486 DX/4",
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[9] = "486 DX/4-WB",
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[14] = "Am5x86-WT",
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[15] = "Am5x86-WB"
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}
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},
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},
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.c_init = init_amd,
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.c_size_cache = amd_size_cache,
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};
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int __init amd_init_cpu(void)
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{
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cpu_devs[X86_VENDOR_AMD] = &amd_cpu_dev;
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return 0;
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}
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//early_arch_initcall(amd_init_cpu);
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static int __init amd_exit_cpu(void)
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{
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cpu_devs[X86_VENDOR_AMD] = NULL;
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return 0;
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}
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late_initcall(amd_exit_cpu);
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