5f8824de8a
The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
111 lines
2 KiB
C
111 lines
2 KiB
C
#ifndef __NVKM_BUS_HWSQ_H__
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#define __NVKM_BUS_HWSQ_H__
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#include <subdev/bus.h>
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struct hwsq {
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struct nvkm_subdev *subdev;
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struct nvkm_hwsq *hwsq;
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int sequence;
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};
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struct hwsq_reg {
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int sequence;
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bool force;
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u32 addr[2];
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u32 data;
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};
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static inline struct hwsq_reg
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hwsq_reg2(u32 addr1, u32 addr2)
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{
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return (struct hwsq_reg) {
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.sequence = 0,
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.force = 0,
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.addr = { addr1, addr2 },
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.data = 0xdeadbeef,
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};
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}
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static inline struct hwsq_reg
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hwsq_reg(u32 addr)
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{
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return hwsq_reg2(addr, addr);
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}
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static inline int
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hwsq_init(struct hwsq *ram, struct nvkm_subdev *subdev)
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{
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struct nvkm_bus *pbus = nvkm_bus(subdev);
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int ret;
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ret = nvkm_hwsq_init(pbus, &ram->hwsq);
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if (ret)
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return ret;
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ram->sequence++;
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ram->subdev = subdev;
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return 0;
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}
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static inline int
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hwsq_exec(struct hwsq *ram, bool exec)
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{
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int ret = 0;
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if (ram->subdev) {
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ret = nvkm_hwsq_fini(&ram->hwsq, exec);
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ram->subdev = NULL;
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}
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return ret;
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}
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static inline u32
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hwsq_rd32(struct hwsq *ram, struct hwsq_reg *reg)
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{
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if (reg->sequence != ram->sequence)
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reg->data = nv_rd32(ram->subdev, reg->addr[0]);
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return reg->data;
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}
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static inline void
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hwsq_wr32(struct hwsq *ram, struct hwsq_reg *reg, u32 data)
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{
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reg->sequence = ram->sequence;
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reg->data = data;
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if (reg->addr[0] != reg->addr[1])
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nvkm_hwsq_wr32(ram->hwsq, reg->addr[1], reg->data);
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nvkm_hwsq_wr32(ram->hwsq, reg->addr[0], reg->data);
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}
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static inline void
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hwsq_nuke(struct hwsq *ram, struct hwsq_reg *reg)
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{
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reg->force = true;
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}
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static inline u32
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hwsq_mask(struct hwsq *ram, struct hwsq_reg *reg, u32 mask, u32 data)
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{
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u32 temp = hwsq_rd32(ram, reg);
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if (temp != ((temp & ~mask) | data) || reg->force)
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hwsq_wr32(ram, reg, (temp & ~mask) | data);
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return temp;
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}
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static inline void
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hwsq_setf(struct hwsq *ram, u8 flag, int data)
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{
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nvkm_hwsq_setf(ram->hwsq, flag, data);
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}
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static inline void
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hwsq_wait(struct hwsq *ram, u8 flag, u8 data)
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{
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nvkm_hwsq_wait(ram->hwsq, flag, data);
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}
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static inline void
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hwsq_nsec(struct hwsq *ram, u32 nsec)
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{
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nvkm_hwsq_nsec(ram->hwsq, nsec);
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}
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#endif
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