867e359b97
This change is the core kernel support for TILEPro and TILE64 chips. No driver support (except the console driver) is included yet. This includes the relevant Linux headers in asm/; the low-level low-level "Tile architecture" headers in arch/, which are shared with the hypervisor, etc., and are build-system agnostic; and the relevant hypervisor headers in hv/. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> Reviewed-by: Paul Mundt <lethal@linux-sh.org>
117 lines
3.5 KiB
C
117 lines
3.5 KiB
C
/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*/
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#ifndef _ASM_TILE_PCI_BRIDGE_H
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#define _ASM_TILE_PCI_BRIDGE_H
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#include <linux/ioport.h>
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#include <linux/pci.h>
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struct device_node;
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struct pci_controller;
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/*
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* pci_io_base returns the memory address at which you can access
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* the I/O space for PCI bus number `bus' (or NULL on error).
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*/
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extern void __iomem *pci_bus_io_base(unsigned int bus);
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extern unsigned long pci_bus_io_base_phys(unsigned int bus);
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extern unsigned long pci_bus_mem_base_phys(unsigned int bus);
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/* Allocate a new PCI host bridge structure */
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extern struct pci_controller *pcibios_alloc_controller(void);
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/* Helper function for setting up resources */
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extern void pci_init_resource(struct resource *res, unsigned long start,
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unsigned long end, int flags, char *name);
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/* Get the PCI host controller for a bus */
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extern struct pci_controller *pci_bus_to_hose(int bus);
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/*
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* Structure of a PCI controller (host bridge)
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*/
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struct pci_controller {
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int index; /* PCI domain number */
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struct pci_bus *root_bus;
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int first_busno;
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int last_busno;
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int hv_cfg_fd[2]; /* config{0,1} fds for this PCIe controller */
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int hv_mem_fd; /* fd to Hypervisor for MMIO operations */
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struct pci_ops *ops;
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int irq_base; /* Base IRQ from the Hypervisor */
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int plx_gen1; /* flag for PLX Gen 1 configuration */
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/* Address ranges that are routed to this controller/bridge. */
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struct resource mem_resources[3];
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};
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static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
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{
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return bus->sysdata;
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}
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extern void setup_indirect_pci_nomap(struct pci_controller *hose,
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void __iomem *cfg_addr, void __iomem *cfg_data);
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extern void setup_indirect_pci(struct pci_controller *hose,
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u32 cfg_addr, u32 cfg_data);
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extern void setup_grackle(struct pci_controller *hose);
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extern unsigned char common_swizzle(struct pci_dev *, unsigned char *);
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/*
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* The following code swizzles for exactly one bridge. The routine
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* common_swizzle below handles multiple bridges. But there are a
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* some boards that don't follow the PCI spec's suggestion so we
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* break this piece out separately.
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*/
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static inline unsigned char bridge_swizzle(unsigned char pin,
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unsigned char idsel)
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{
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return (((pin-1) + idsel) % 4) + 1;
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}
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/*
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* The following macro is used to lookup irqs in a standard table
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* format for those PPC systems that do not already have PCI
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* interrupts properly routed.
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*/
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/* FIXME - double check this */
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#define PCI_IRQ_TABLE_LOOKUP ({ \
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long _ctl_ = -1; \
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if (idsel >= min_idsel && idsel <= max_idsel && pin <= irqs_per_slot) \
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_ctl_ = pci_irq_table[idsel - min_idsel][pin-1]; \
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_ctl_; \
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})
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/*
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* Scan the buses below a given PCI host bridge and assign suitable
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* resources to all devices found.
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*/
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extern int pciauto_bus_scan(struct pci_controller *, int);
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#ifdef CONFIG_PCI
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extern unsigned long pci_address_to_pio(phys_addr_t address);
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#else
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static inline unsigned long pci_address_to_pio(phys_addr_t address)
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{
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return (unsigned long)-1;
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}
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#endif
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#endif /* _ASM_TILE_PCI_BRIDGE_H */
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