ff5a3b509e
Move the HIPPI driver into drivers/net/hippi/ and make the necessary Kconfig and Makefile changes. CC: Jes Sorensen <jes@wildopensource.com> CC: Jes Sorensen <jes@trained-monkey.org> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
846 lines
15 KiB
C
846 lines
15 KiB
C
#ifndef _RRUNNER_H_
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#define _RRUNNER_H_
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#include <linux/interrupt.h>
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#if ((BITS_PER_LONG != 32) && (BITS_PER_LONG != 64))
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#error "BITS_PER_LONG not defined or not valid"
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#endif
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struct rr_regs {
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u32 pad0[16];
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u32 HostCtrl;
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u32 LocalCtrl;
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u32 Pc;
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u32 BrkPt;
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/* Timer increments every 0.97 micro-seconds (unsigned int) */
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u32 Timer_Hi;
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u32 Timer;
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u32 TimerRef;
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u32 PciState;
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u32 Event;
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u32 MbEvent;
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u32 WinBase;
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u32 WinData;
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u32 RX_state;
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u32 TX_state;
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u32 Overhead;
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u32 ExtIo;
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u32 DmaWriteHostHi;
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u32 DmaWriteHostLo;
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u32 pad1[2];
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u32 DmaReadHostHi;
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u32 DmaReadHostLo;
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u32 pad2;
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u32 DmaReadLen;
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u32 DmaWriteState;
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u32 DmaWriteLcl;
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u32 DmaWriteIPchecksum;
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u32 DmaWriteLen;
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u32 DmaReadState;
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u32 DmaReadLcl;
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u32 DmaReadIPchecksum;
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u32 pad3;
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u32 RxBase;
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u32 RxPrd;
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u32 RxCon;
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u32 pad4;
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u32 TxBase;
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u32 TxPrd;
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u32 TxCon;
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u32 pad5;
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u32 RxIndPro;
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u32 RxIndCon;
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u32 RxIndRef;
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u32 pad6;
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u32 TxIndPro;
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u32 TxIndCon;
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u32 TxIndRef;
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u32 pad7[17];
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u32 DrCmndPro;
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u32 DrCmndCon;
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u32 DrCmndRef;
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u32 pad8;
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u32 DwCmndPro;
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u32 DwCmndCon;
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u32 DwCmndRef;
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u32 AssistState;
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u32 DrDataPro;
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u32 DrDataCon;
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u32 DrDataRef;
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u32 pad9;
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u32 DwDataPro;
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u32 DwDataCon;
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u32 DwDataRef;
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u32 pad10[33];
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u32 EvtCon;
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u32 pad11[5];
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u32 TxPi;
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u32 IpRxPi;
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u32 pad11a[8];
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u32 CmdRing[16];
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/* The ULA is in two registers the high order two bytes of the first
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* word contain the RunCode features.
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* ula0 res res byte0 byte1
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* ula1 byte2 byte3 byte4 byte5
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*/
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u32 Ula0;
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u32 Ula1;
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u32 RxRingHi;
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u32 RxRingLo;
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u32 InfoPtrHi;
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u32 InfoPtrLo;
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u32 Mode;
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u32 ConRetry;
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u32 ConRetryTmr;
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u32 ConTmout;
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u32 CtatTmr;
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u32 MaxRxRng;
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u32 IntrTmr;
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u32 TxDataMvTimeout;
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u32 RxDataMvTimeout;
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u32 EvtPrd;
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u32 TraceIdx;
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u32 Fail1;
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u32 Fail2;
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u32 DrvPrm;
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u32 FilterLA;
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u32 FwRev;
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u32 FwRes1;
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u32 FwRes2;
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u32 FwRes3;
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u32 WriteDmaThresh;
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u32 ReadDmaThresh;
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u32 pad12[325];
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u32 Window[512];
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};
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/*
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* Host control register bits.
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*/
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#define RR_INT 0x01
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#define RR_CLEAR_INT 0x02
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#define NO_SWAP 0x04000004
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#define NO_SWAP1 0x00000004
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#define PCI_RESET_NIC 0x08
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#define HALT_NIC 0x10
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#define SSTEP_NIC 0x20
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#define MEM_READ_MULTI 0x40
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#define NIC_HALTED 0x100
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#define HALT_INST 0x200
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#define PARITY_ERR 0x400
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#define INVALID_INST_B 0x800
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#define RR_REV_2 0x20000000
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#define RR_REV_MASK 0xf0000000
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/*
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* Local control register bits.
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*/
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#define INTA_STATE 0x01
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#define CLEAR_INTA 0x02
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#define FAST_EEPROM_ACCESS 0x08
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#define ENABLE_EXTRA_SRAM 0x100
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#define ENABLE_EXTRA_DESC 0x200
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#define ENABLE_PARITY 0x400
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#define FORCE_DMA_PARITY_ERROR 0x800
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#define ENABLE_EEPROM_WRITE 0x1000
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#define ENABLE_DATA_CACHE 0x2000
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#define SRAM_LO_PARITY_ERR 0x4000
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#define SRAM_HI_PARITY_ERR 0x8000
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/*
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* PCI state bits.
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*/
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#define FORCE_PCI_RESET 0x01
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#define PROVIDE_LENGTH 0x02
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#define MASK_DMA_READ_MAX 0x1C
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#define RBURST_DISABLE 0x00
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#define RBURST_4 0x04
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#define RBURST_16 0x08
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#define RBURST_32 0x0C
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#define RBURST_64 0x10
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#define RBURST_128 0x14
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#define RBURST_256 0x18
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#define RBURST_1024 0x1C
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#define MASK_DMA_WRITE_MAX 0xE0
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#define WBURST_DISABLE 0x00
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#define WBURST_4 0x20
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#define WBURST_16 0x40
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#define WBURST_32 0x60
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#define WBURST_64 0x80
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#define WBURST_128 0xa0
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#define WBURST_256 0xc0
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#define WBURST_1024 0xe0
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#define MASK_MIN_DMA 0xFF00
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#define FIFO_RETRY_ENABLE 0x10000
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/*
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* Event register
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*/
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#define DMA_WRITE_DONE 0x10000
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#define DMA_READ_DONE 0x20000
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#define DMA_WRITE_ERR 0x40000
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#define DMA_READ_ERR 0x80000
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/*
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* Receive state
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*
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* RoadRunner HIPPI Receive State Register controls and monitors the
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* HIPPI receive interface in the NIC. Look at err bits when a HIPPI
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* receive Error Event occurs.
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*/
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#define ENABLE_NEW_CON 0x01
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#define RESET_RECV 0x02
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#define RECV_ALL 0x00
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#define RECV_1K 0x20
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#define RECV_2K 0x40
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#define RECV_4K 0x60
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#define RECV_8K 0x80
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#define RECV_16K 0xa0
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#define RECV_32K 0xc0
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#define RECV_64K 0xe0
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/*
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* Transmit status.
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*/
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#define ENA_XMIT 0x01
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#define PERM_CON 0x02
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/*
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* DMA write state
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*/
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#define RESET_DMA 0x01
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#define NO_SWAP_DMA 0x02
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#define DMA_ACTIVE 0x04
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#define THRESH_MASK 0x1F
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#define DMA_ERROR_MASK 0xff000000
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/*
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* Gooddies stored in the ULA registers.
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*/
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#define TRACE_ON_WHAT_BIT 0x00020000 /* Traces on */
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#define ONEM_BUF_WHAT_BIT 0x00040000 /* 1Meg vs 256K */
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#define CHAR_API_WHAT_BIT 0x00080000 /* Char API vs network only */
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#define CMD_EVT_WHAT_BIT 0x00200000 /* Command event */
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#define LONG_TX_WHAT_BIT 0x00400000
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#define LONG_RX_WHAT_BIT 0x00800000
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#define WHAT_BIT_MASK 0xFFFD0000 /* Feature bit mask */
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/*
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* Mode status
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*/
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#define EVENT_OVFL 0x80000000
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#define FATAL_ERR 0x40000000
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#define LOOP_BACK 0x01
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#define MODE_PH 0x02
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#define MODE_FP 0x00
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#define PTR64BIT 0x04
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#define PTR32BIT 0x00
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#define PTR_WD_SWAP 0x08
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#define PTR_WD_NOSWAP 0x00
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#define POST_WARN_EVENT 0x10
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#define ERR_TERM 0x20
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#define DIRECT_CONN 0x40
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#define NO_NIC_WATCHDOG 0x80
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#define SWAP_DATA 0x100
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#define SWAP_CONTROL 0x200
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#define NIC_HALT_ON_ERR 0x400
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#define NIC_NO_RESTART 0x800
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#define HALF_DUP_TX 0x1000
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#define HALF_DUP_RX 0x2000
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/*
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* Error codes
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*/
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/* Host Error Codes - values of fail1 */
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#define ERR_UNKNOWN_MBOX 0x1001
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#define ERR_UNKNOWN_CMD 0x1002
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#define ERR_MAX_RING 0x1003
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#define ERR_RING_CLOSED 0x1004
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#define ERR_RING_OPEN 0x1005
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/* Firmware internal errors */
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#define ERR_EVENT_RING_FULL 0x01
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#define ERR_DW_PEND_CMND_FULL 0x02
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#define ERR_DR_PEND_CMND_FULL 0x03
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#define ERR_DW_PEND_DATA_FULL 0x04
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#define ERR_DR_PEND_DATA_FULL 0x05
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#define ERR_ILLEGAL_JUMP 0x06
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#define ERR_UNIMPLEMENTED 0x07
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#define ERR_TX_INFO_FULL 0x08
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#define ERR_RX_INFO_FULL 0x09
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#define ERR_ILLEGAL_MODE 0x0A
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#define ERR_MAIN_TIMEOUT 0x0B
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#define ERR_EVENT_BITS 0x0C
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#define ERR_UNPEND_FULL 0x0D
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#define ERR_TIMER_QUEUE_FULL 0x0E
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#define ERR_TIMER_QUEUE_EMPTY 0x0F
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#define ERR_TIMER_NO_FREE 0x10
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#define ERR_INTR_START 0x11
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#define ERR_BAD_STARTUP 0x12
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#define ERR_NO_PKT_END 0x13
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#define ERR_HALTED_ON_ERR 0x14
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/* Hardware NIC Errors */
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#define ERR_WRITE_DMA 0x0101
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#define ERR_READ_DMA 0x0102
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#define ERR_EXT_SERIAL 0x0103
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#define ERR_TX_INT_PARITY 0x0104
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/*
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* Event definitions
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*/
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#define EVT_RING_ENTRIES 64
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#define EVT_RING_SIZE (EVT_RING_ENTRIES * sizeof(struct event))
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struct event {
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#ifdef __LITTLE_ENDIAN
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u16 index;
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u8 ring;
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u8 code;
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#else
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u8 code;
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u8 ring;
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u16 index;
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#endif
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u32 timestamp;
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};
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/*
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* General Events
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*/
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#define E_NIC_UP 0x01
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#define E_WATCHDOG 0x02
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#define E_STAT_UPD 0x04
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#define E_INVAL_CMD 0x05
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#define E_SET_CMD_CONS 0x06
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#define E_LINK_ON 0x07
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#define E_LINK_OFF 0x08
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#define E_INTERN_ERR 0x09
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#define E_HOST_ERR 0x0A
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#define E_STATS_UPDATE 0x0B
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#define E_REJECTING 0x0C
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/*
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* Send Events
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*/
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#define E_CON_REJ 0x13
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#define E_CON_TMOUT 0x14
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#define E_CON_NC_TMOUT 0x15 /* I , Connection No Campon Timeout */
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#define E_DISC_ERR 0x16
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#define E_INT_PRTY 0x17
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#define E_TX_IDLE 0x18
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#define E_TX_LINK_DROP 0x19
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#define E_TX_INV_RNG 0x1A
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#define E_TX_INV_BUF 0x1B
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#define E_TX_INV_DSC 0x1C
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/*
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* Destination Events
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*/
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/*
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* General Receive events
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*/
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#define E_VAL_RNG 0x20
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#define E_RX_RNG_ENER 0x21
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#define E_INV_RNG 0x22
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#define E_RX_RNG_SPC 0x23
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#define E_RX_RNG_OUT 0x24
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#define E_PKT_DISCARD 0x25
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#define E_INFO_EVT 0x27
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/*
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* Data corrupted events
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*/
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#define E_RX_PAR_ERR 0x2B
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#define E_RX_LLRC_ERR 0x2C
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#define E_IP_CKSM_ERR 0x2D
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#define E_DTA_CKSM_ERR 0x2E
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#define E_SHT_BST 0x2F
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/*
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* Data lost events
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*/
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#define E_LST_LNK_ERR 0x30
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#define E_FLG_SYN_ERR 0x31
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#define E_FRM_ERR 0x32
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#define E_RX_IDLE 0x33
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#define E_PKT_LN_ERR 0x34
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#define E_STATE_ERR 0x35
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#define E_UNEXP_DATA 0x3C
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/*
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* Fatal events
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*/
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#define E_RX_INV_BUF 0x36
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#define E_RX_INV_DSC 0x37
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#define E_RNG_BLK 0x38
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/*
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* Warning events
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*/
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#define E_RX_TO 0x39
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#define E_BFR_SPC 0x3A
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#define E_INV_ULP 0x3B
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#define E_NOT_IMPLEMENTED 0x40
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/*
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* Commands
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*/
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#define CMD_RING_ENTRIES 16
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struct cmd {
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#ifdef __LITTLE_ENDIAN
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u16 index;
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u8 ring;
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u8 code;
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#else
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u8 code;
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u8 ring;
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u16 index;
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#endif
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};
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#define C_START_FW 0x01
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#define C_UPD_STAT 0x02
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#define C_WATCHDOG 0x05
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#define C_DEL_RNG 0x09
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#define C_NEW_RNG 0x0A
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#define C_CONN 0x0D
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/*
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* Mode bits
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*/
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#define PACKET_BAD 0x01 /* Packet had link-layer error */
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#define INTERRUPT 0x02
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#define TX_IP_CKSUM 0x04
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#define PACKET_END 0x08
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#define PACKET_START 0x10
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#define SAME_IFIELD 0x80
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typedef struct {
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#if (BITS_PER_LONG == 64)
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u64 addrlo;
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#else
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u32 addrhi;
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u32 addrlo;
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#endif
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} rraddr;
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static inline void set_rraddr(rraddr *ra, dma_addr_t addr)
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{
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unsigned long baddr = addr;
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#if (BITS_PER_LONG == 64)
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ra->addrlo = baddr;
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#else
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/* Don't bother setting zero every time */
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ra->addrlo = baddr;
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#endif
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mb();
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}
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static inline void set_rxaddr(struct rr_regs __iomem *regs, volatile dma_addr_t addr)
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{
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unsigned long baddr = addr;
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#if (BITS_PER_LONG == 64) && defined(__LITTLE_ENDIAN)
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writel(baddr & 0xffffffff, ®s->RxRingHi);
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writel(baddr >> 32, ®s->RxRingLo);
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#elif (BITS_PER_LONG == 64)
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writel(baddr >> 32, ®s->RxRingHi);
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writel(baddr & 0xffffffff, ®s->RxRingLo);
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#else
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writel(0, ®s->RxRingHi);
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writel(baddr, ®s->RxRingLo);
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#endif
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mb();
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}
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static inline void set_infoaddr(struct rr_regs __iomem *regs, volatile dma_addr_t addr)
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{
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unsigned long baddr = addr;
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#if (BITS_PER_LONG == 64) && defined(__LITTLE_ENDIAN)
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writel(baddr & 0xffffffff, ®s->InfoPtrHi);
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writel(baddr >> 32, ®s->InfoPtrLo);
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#elif (BITS_PER_LONG == 64)
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writel(baddr >> 32, ®s->InfoPtrHi);
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writel(baddr & 0xffffffff, ®s->InfoPtrLo);
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#else
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writel(0, ®s->InfoPtrHi);
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writel(baddr, ®s->InfoPtrLo);
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#endif
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mb();
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}
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/*
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* TX ring
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*/
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#ifdef CONFIG_ROADRUNNER_LARGE_RINGS
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#define TX_RING_ENTRIES 32
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#else
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#define TX_RING_ENTRIES 16
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#endif
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#define TX_TOTAL_SIZE (TX_RING_ENTRIES * sizeof(struct tx_desc))
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struct tx_desc{
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rraddr addr;
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u32 res;
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#ifdef __LITTLE_ENDIAN
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u16 size;
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u8 pad;
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u8 mode;
|
|
#else
|
|
u8 mode;
|
|
u8 pad;
|
|
u16 size;
|
|
#endif
|
|
};
|
|
|
|
|
|
#ifdef CONFIG_ROADRUNNER_LARGE_RINGS
|
|
#define RX_RING_ENTRIES 32
|
|
#else
|
|
#define RX_RING_ENTRIES 16
|
|
#endif
|
|
#define RX_TOTAL_SIZE (RX_RING_ENTRIES * sizeof(struct rx_desc))
|
|
|
|
struct rx_desc{
|
|
rraddr addr;
|
|
u32 res;
|
|
#ifdef __LITTLE_ENDIAN
|
|
u16 size;
|
|
u8 pad;
|
|
u8 mode;
|
|
#else
|
|
u8 mode;
|
|
u8 pad;
|
|
u16 size;
|
|
#endif
|
|
};
|
|
|
|
|
|
/*
|
|
* ioctl's
|
|
*/
|
|
|
|
#define SIOCRRPFW SIOCDEVPRIVATE /* put firmware */
|
|
#define SIOCRRGFW SIOCDEVPRIVATE+1 /* get firmware */
|
|
#define SIOCRRID SIOCDEVPRIVATE+2 /* identify */
|
|
|
|
|
|
struct seg_hdr {
|
|
u32 seg_start;
|
|
u32 seg_len;
|
|
u32 seg_eestart;
|
|
};
|
|
|
|
|
|
#define EEPROM_BASE 0x80000000
|
|
#define EEPROM_WORDS 8192
|
|
#define EEPROM_BYTES (EEPROM_WORDS * sizeof(u32))
|
|
|
|
struct eeprom_boot {
|
|
u32 key1;
|
|
u32 key2;
|
|
u32 sram_size;
|
|
struct seg_hdr loader;
|
|
u32 init_chksum;
|
|
u32 reserved1;
|
|
};
|
|
|
|
struct eeprom_manf {
|
|
u32 HeaderFmt;
|
|
u32 Firmware;
|
|
u32 BoardRevision;
|
|
u32 RoadrunnerRev;
|
|
char OpticsPart[8];
|
|
u32 OpticsRev;
|
|
u32 pad1;
|
|
char SramPart[8];
|
|
u32 SramRev;
|
|
u32 pad2;
|
|
char EepromPart[8];
|
|
u32 EepromRev;
|
|
u32 EepromSize;
|
|
char PalPart[8];
|
|
u32 PalRev;
|
|
u32 pad3;
|
|
char PalCodeFile[12];
|
|
u32 PalCodeRev;
|
|
char BoardULA[8];
|
|
char SerialNo[8];
|
|
char MfgDate[8];
|
|
char MfgTime[8];
|
|
char ModifyDate[8];
|
|
u32 ModCount;
|
|
u32 pad4[13];
|
|
};
|
|
|
|
|
|
struct eeprom_phase_info {
|
|
char phase1File[12];
|
|
u32 phase1Rev;
|
|
char phase1Date[8];
|
|
char phase2File[12];
|
|
u32 phase2Rev;
|
|
char phase2Date[8];
|
|
u32 reserved7[4];
|
|
};
|
|
|
|
struct eeprom_rncd_info {
|
|
u32 FwStart;
|
|
u32 FwRev;
|
|
char FwDate[8];
|
|
u32 AddrRunCodeSegs;
|
|
u32 FileNames;
|
|
char File[13][8];
|
|
};
|
|
|
|
|
|
/* Phase 1 region (starts are word offset 0x80) */
|
|
struct phase1_hdr{
|
|
u32 jump;
|
|
u32 noop;
|
|
struct seg_hdr phase2Seg;
|
|
};
|
|
|
|
struct eeprom {
|
|
struct eeprom_boot boot;
|
|
u32 pad1[8];
|
|
struct eeprom_manf manf;
|
|
struct eeprom_phase_info phase_info;
|
|
struct eeprom_rncd_info rncd_info;
|
|
u32 pad2[15];
|
|
u32 hdr_checksum;
|
|
struct phase1_hdr phase1;
|
|
};
|
|
|
|
|
|
struct rr_stats {
|
|
u32 NicTimeStamp;
|
|
u32 RngCreated;
|
|
u32 RngDeleted;
|
|
u32 IntrGen;
|
|
u32 NEvtOvfl;
|
|
u32 InvCmd;
|
|
u32 DmaReadErrs;
|
|
u32 DmaWriteErrs;
|
|
u32 StatUpdtT;
|
|
u32 StatUpdtC;
|
|
u32 WatchDog;
|
|
u32 Trace;
|
|
|
|
/* Serial HIPPI */
|
|
u32 LnkRdyEst;
|
|
u32 GLinkErr;
|
|
u32 AltFlgErr;
|
|
u32 OvhdBit8Sync;
|
|
u32 RmtSerPrtyErr;
|
|
u32 RmtParPrtyErr;
|
|
u32 RmtLoopBk;
|
|
u32 pad1;
|
|
|
|
/* HIPPI tx */
|
|
u32 ConEst;
|
|
u32 ConRejS;
|
|
u32 ConRetry;
|
|
u32 ConTmOut;
|
|
u32 SndConDiscon;
|
|
u32 SndParErr;
|
|
u32 PktSnt;
|
|
u32 pad2[2];
|
|
u32 ShFBstSnt;
|
|
u64 BytSent;
|
|
u32 TxTimeout;
|
|
u32 pad3[3];
|
|
|
|
/* HIPPI rx */
|
|
u32 ConAcc;
|
|
u32 ConRejdiPrty;
|
|
u32 ConRejd64b;
|
|
u32 ConRejdBuf;
|
|
u32 RxConDiscon;
|
|
u32 RxConNoData;
|
|
u32 PktRx;
|
|
u32 pad4[2];
|
|
u32 ShFBstRx;
|
|
u64 BytRx;
|
|
u32 RxParErr;
|
|
u32 RxLLRCerr;
|
|
u32 RxBstSZerr;
|
|
u32 RxStateErr;
|
|
u32 RxRdyErr;
|
|
u32 RxInvULP;
|
|
u32 RxSpcBuf;
|
|
u32 RxSpcDesc;
|
|
u32 RxRngSpc;
|
|
u32 RxRngFull;
|
|
u32 RxPktLenErr;
|
|
u32 RxCksmErr;
|
|
u32 RxPktDrp;
|
|
u32 RngLowSpc;
|
|
u32 RngDataClose;
|
|
u32 RxTimeout;
|
|
u32 RxIdle;
|
|
};
|
|
|
|
|
|
/*
|
|
* This struct is shared with the NIC firmware.
|
|
*/
|
|
struct ring_ctrl {
|
|
rraddr rngptr;
|
|
#ifdef __LITTLE_ENDIAN
|
|
u16 entries;
|
|
u8 pad;
|
|
u8 entry_size;
|
|
u16 pi;
|
|
u16 mode;
|
|
#else
|
|
u8 entry_size;
|
|
u8 pad;
|
|
u16 entries;
|
|
u16 mode;
|
|
u16 pi;
|
|
#endif
|
|
};
|
|
|
|
struct rr_info {
|
|
union {
|
|
struct rr_stats stats;
|
|
u32 stati[128];
|
|
} s;
|
|
struct ring_ctrl evt_ctrl;
|
|
struct ring_ctrl cmd_ctrl;
|
|
struct ring_ctrl tx_ctrl;
|
|
u8 pad[464];
|
|
u8 trace[3072];
|
|
};
|
|
|
|
/*
|
|
* The linux structure for the RoadRunner.
|
|
*
|
|
* RX/TX descriptors are put first to make sure they are properly
|
|
* aligned and do not cross cache-line boundaries.
|
|
*/
|
|
|
|
struct rr_private
|
|
{
|
|
struct rx_desc *rx_ring;
|
|
struct tx_desc *tx_ring;
|
|
struct event *evt_ring;
|
|
dma_addr_t tx_ring_dma;
|
|
dma_addr_t rx_ring_dma;
|
|
dma_addr_t evt_ring_dma;
|
|
/* Alignment ok ? */
|
|
struct sk_buff *rx_skbuff[RX_RING_ENTRIES];
|
|
struct sk_buff *tx_skbuff[TX_RING_ENTRIES];
|
|
struct rr_regs __iomem *regs; /* Register base */
|
|
struct ring_ctrl *rx_ctrl; /* Receive ring control */
|
|
struct rr_info *info; /* Shared info page */
|
|
dma_addr_t rx_ctrl_dma;
|
|
dma_addr_t info_dma;
|
|
spinlock_t lock;
|
|
struct timer_list timer;
|
|
u32 cur_rx, cur_cmd, cur_evt;
|
|
u32 dirty_rx, dirty_tx;
|
|
u32 tx_full;
|
|
u32 fw_rev;
|
|
volatile short fw_running;
|
|
struct pci_dev *pci_dev;
|
|
};
|
|
|
|
|
|
/*
|
|
* Prototypes
|
|
*/
|
|
static int rr_init(struct net_device *dev);
|
|
static int rr_init1(struct net_device *dev);
|
|
static irqreturn_t rr_interrupt(int irq, void *dev_id);
|
|
|
|
static int rr_open(struct net_device *dev);
|
|
static netdev_tx_t rr_start_xmit(struct sk_buff *skb,
|
|
struct net_device *dev);
|
|
static int rr_close(struct net_device *dev);
|
|
static int rr_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
|
|
static unsigned int rr_read_eeprom(struct rr_private *rrpriv,
|
|
unsigned long offset,
|
|
unsigned char *buf,
|
|
unsigned long length);
|
|
static u32 rr_read_eeprom_word(struct rr_private *rrpriv, size_t offset);
|
|
static int rr_load_firmware(struct net_device *dev);
|
|
static inline void rr_raz_tx(struct rr_private *, struct net_device *);
|
|
static inline void rr_raz_rx(struct rr_private *, struct net_device *);
|
|
#endif /* _RRUNNER_H_ */
|