988addf82e
Conflicts: arch/arm/mach-mx2/devices.c arch/arm/mach-mx2/devices.h sound/soc/pxa/pxa-ssp.c
508 lines
13 KiB
C
508 lines
13 KiB
C
/*
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* Author: MontaVista Software, Inc.
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* <source@mvista.com>
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*
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* Based on the OMAP devices.c
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*
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* 2005 (c) MontaVista Software, Inc. This file is licensed under the
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* terms of the GNU General Public License version 2. This program is
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* licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*
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* Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/gpio.h>
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#include <linux/dma-mapping.h>
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#include <mach/irqs.h>
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#include <mach/hardware.h>
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#include <mach/common.h>
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#include <mach/mmc.h>
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#include "devices.h"
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/*
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* SPI master controller
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*
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* - i.MX1: 2 channel (slighly different register setting)
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* - i.MX21: 2 channel
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* - i.MX27: 3 channel
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*/
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#define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq) \
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static struct resource mxc_spi_resources ## n[] = { \
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{ \
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.start = baseaddr, \
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.end = baseaddr + SZ_4K - 1, \
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.flags = IORESOURCE_MEM, \
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}, { \
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.start = irq, \
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.end = irq, \
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.flags = IORESOURCE_IRQ, \
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}, \
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}; \
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\
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struct platform_device mxc_spi_device ## n = { \
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.name = "spi_imx", \
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.id = n, \
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.num_resources = ARRAY_SIZE(mxc_spi_resources ## n), \
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.resource = mxc_spi_resources ## n, \
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}
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DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR, MX2x_INT_CSPI1);
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DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR, MX2x_INT_CSPI2);
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#ifdef CONFIG_MACH_MX27
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DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR, MX27_INT_CSPI3);
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#endif
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/*
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* General Purpose Timer
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* - i.MX21: 3 timers
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* - i.MX27: 6 timers
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*/
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#define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq) \
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static struct resource timer ## n ##_resources[] = { \
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{ \
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.start = baseaddr, \
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.end = baseaddr + SZ_4K - 1, \
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.flags = IORESOURCE_MEM, \
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}, { \
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.start = irq, \
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.end = irq, \
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.flags = IORESOURCE_IRQ, \
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} \
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}; \
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\
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struct platform_device mxc_gpt ## n = { \
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.name = "imx_gpt", \
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.id = n, \
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.num_resources = ARRAY_SIZE(timer ## n ## _resources), \
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.resource = timer ## n ## _resources, \
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}
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/* We use gpt1 as system timer, so do not add a device for this one */
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DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR, MX2x_INT_GPT2);
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DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR, MX2x_INT_GPT3);
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#ifdef CONFIG_MACH_MX27
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DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR, MX27_INT_GPT4);
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DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5);
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DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6);
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#endif
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/*
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* Watchdog:
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* - i.MX1
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* - i.MX21
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* - i.MX27
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*/
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static struct resource mxc_wdt_resources[] = {
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{
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.start = MX2x_WDOG_BASE_ADDR,
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.end = MX2x_WDOG_BASE_ADDR + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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struct platform_device mxc_wdt = {
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.name = "mxc_wdt",
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.id = 0,
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.num_resources = ARRAY_SIZE(mxc_wdt_resources),
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.resource = mxc_wdt_resources,
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};
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static struct resource mxc_w1_master_resources[] = {
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{
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.start = MX2x_OWIRE_BASE_ADDR,
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.end = MX2x_OWIRE_BASE_ADDR + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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struct platform_device mxc_w1_master_device = {
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.name = "mxc_w1",
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.id = 0,
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.num_resources = ARRAY_SIZE(mxc_w1_master_resources),
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.resource = mxc_w1_master_resources,
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};
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#define DEFINE_MXC_NAND_DEVICE(pfx, baseaddr, irq) \
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static struct resource pfx ## _nand_resources[] = { \
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{ \
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.start = baseaddr, \
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.end = baseaddr + SZ_4K - 1, \
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.flags = IORESOURCE_MEM, \
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}, { \
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.start = irq, \
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.end = irq, \
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.flags = IORESOURCE_IRQ, \
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}, \
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}; \
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\
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struct platform_device pfx ## _nand_device = { \
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.name = "mxc_nand", \
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.id = 0, \
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.num_resources = ARRAY_SIZE(pfx ## _nand_resources), \
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.resource = pfx ## _nand_resources, \
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}
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#ifdef CONFIG_MACH_MX21
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DEFINE_MXC_NAND_DEVICE(imx21, MX21_NFC_BASE_ADDR, MX21_INT_NANDFC);
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#endif
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#ifdef CONFIG_MACH_MX27
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DEFINE_MXC_NAND_DEVICE(imx27, MX27_NFC_BASE_ADDR, MX27_INT_NANDFC);
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#endif
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/*
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* lcdc:
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* - i.MX1: the basic controller
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* - i.MX21: to be checked
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* - i.MX27: like i.MX1, with slightly variations
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*/
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static struct resource mxc_fb[] = {
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{
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.start = MX2x_LCDC_BASE_ADDR,
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.end = MX2x_LCDC_BASE_ADDR + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MX2x_INT_LCDC,
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.end = MX2x_INT_LCDC,
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.flags = IORESOURCE_IRQ,
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}
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};
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/* mxc lcd driver */
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struct platform_device mxc_fb_device = {
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.name = "imx-fb",
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.id = 0,
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.num_resources = ARRAY_SIZE(mxc_fb),
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.resource = mxc_fb,
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.dev = {
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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};
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#ifdef CONFIG_MACH_MX27
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static struct resource mxc_fec_resources[] = {
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{
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.start = MX27_FEC_BASE_ADDR,
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.end = MX27_FEC_BASE_ADDR + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MX27_INT_FEC,
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.end = MX27_INT_FEC,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct platform_device mxc_fec_device = {
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.name = "fec",
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.id = 0,
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.num_resources = ARRAY_SIZE(mxc_fec_resources),
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.resource = mxc_fec_resources,
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};
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#endif
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#define DEFINE_IMX_I2C_DEVICE(n, baseaddr, irq) \
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static struct resource mxc_i2c_resources ## n[] = { \
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{ \
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.start = baseaddr, \
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.end = baseaddr + SZ_4K - 1, \
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.flags = IORESOURCE_MEM, \
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}, { \
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.start = irq, \
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.end = irq, \
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.flags = IORESOURCE_IRQ, \
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} \
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}; \
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\
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struct platform_device mxc_i2c_device ## n = { \
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.name = "imx-i2c", \
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.id = n, \
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.num_resources = ARRAY_SIZE(mxc_i2c_resources ## n), \
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.resource = mxc_i2c_resources ## n, \
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}
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DEFINE_IMX_I2C_DEVICE(0, MX2x_I2C_BASE_ADDR, MX2x_INT_I2C);
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#ifdef CONFIG_MACH_MX27
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DEFINE_IMX_I2C_DEVICE(1, MX27_I2C2_BASE_ADDR, MX27_INT_I2C2);
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#endif
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static struct resource mxc_pwm_resources[] = {
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{
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.start = MX2x_PWM_BASE_ADDR,
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.end = MX2x_PWM_BASE_ADDR + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MX2x_INT_PWM,
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.end = MX2x_INT_PWM,
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.flags = IORESOURCE_IRQ,
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}
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};
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struct platform_device mxc_pwm_device = {
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.name = "mxc_pwm",
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.id = 0,
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.num_resources = ARRAY_SIZE(mxc_pwm_resources),
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.resource = mxc_pwm_resources,
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};
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#define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq) \
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static struct resource mxc_sdhc_resources ## n[] = { \
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{ \
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.start = baseaddr, \
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.end = baseaddr + SZ_4K - 1, \
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.flags = IORESOURCE_MEM, \
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}, { \
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.start = irq, \
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.end = irq, \
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.flags = IORESOURCE_IRQ, \
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}, { \
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.start = dmareq, \
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.end = dmareq, \
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.flags = IORESOURCE_DMA, \
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}, \
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}; \
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\
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static u64 mxc_sdhc ## n ## _dmamask = DMA_BIT_MASK(32); \
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\
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struct platform_device mxc_sdhc_device ## n = { \
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.name = "mxc-mmc", \
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.id = n, \
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.dev = { \
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.dma_mask = &mxc_sdhc ## n ## _dmamask, \
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.coherent_dma_mask = DMA_BIT_MASK(32), \
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}, \
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.num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n), \
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.resource = mxc_sdhc_resources ## n, \
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}
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DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR, MX2x_INT_SDHC1, MX2x_DMA_REQ_SDHC1);
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DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR, MX2x_INT_SDHC2, MX2x_DMA_REQ_SDHC2);
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#ifdef CONFIG_MACH_MX27
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static struct resource otg_resources[] = {
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{
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.start = MX27_USBOTG_BASE_ADDR,
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.end = MX27_USBOTG_BASE_ADDR + 0x1ff,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MX27_INT_USB3,
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.end = MX27_INT_USB3,
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.flags = IORESOURCE_IRQ,
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},
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};
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static u64 otg_dmamask = DMA_BIT_MASK(32);
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/* OTG gadget device */
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struct platform_device mxc_otg_udc_device = {
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.name = "fsl-usb2-udc",
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.id = -1,
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.dev = {
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.dma_mask = &otg_dmamask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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.resource = otg_resources,
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.num_resources = ARRAY_SIZE(otg_resources),
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};
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/* OTG host */
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struct platform_device mxc_otg_host = {
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.name = "mxc-ehci",
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.id = 0,
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.dev = {
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.coherent_dma_mask = DMA_BIT_MASK(32),
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.dma_mask = &otg_dmamask,
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},
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.resource = otg_resources,
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.num_resources = ARRAY_SIZE(otg_resources),
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};
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/* USB host 1 */
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static u64 usbh1_dmamask = DMA_BIT_MASK(32);
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static struct resource mxc_usbh1_resources[] = {
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{
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.start = MX27_USBOTG_BASE_ADDR + 0x200,
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.end = MX27_USBOTG_BASE_ADDR + 0x3ff,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MX27_INT_USB1,
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.end = MX27_INT_USB1,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct platform_device mxc_usbh1 = {
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.name = "mxc-ehci",
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.id = 1,
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.dev = {
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.coherent_dma_mask = DMA_BIT_MASK(32),
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.dma_mask = &usbh1_dmamask,
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},
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.resource = mxc_usbh1_resources,
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.num_resources = ARRAY_SIZE(mxc_usbh1_resources),
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};
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/* USB host 2 */
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static u64 usbh2_dmamask = DMA_BIT_MASK(32);
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static struct resource mxc_usbh2_resources[] = {
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{
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.start = MX27_USBOTG_BASE_ADDR + 0x400,
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.end = MX27_USBOTG_BASE_ADDR + 0x5ff,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MX27_INT_USB2,
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.end = MX27_INT_USB2,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct platform_device mxc_usbh2 = {
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.name = "mxc-ehci",
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.id = 2,
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.dev = {
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.coherent_dma_mask = DMA_BIT_MASK(32),
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.dma_mask = &usbh2_dmamask,
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},
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.resource = mxc_usbh2_resources,
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.num_resources = ARRAY_SIZE(mxc_usbh2_resources),
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};
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#endif
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#define DEFINE_IMX_SSI_DMARES(_name, ssin, suffix) \
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{ \
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.name = _name, \
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.start = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
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.end = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
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.flags = IORESOURCE_DMA, \
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}
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#define DEFINE_IMX_SSI_DEVICE(n, ssin, baseaddr, irq) \
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static struct resource imx_ssi_resources ## n[] = { \
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{ \
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.start = MX2x_SSI ## ssin ## _BASE_ADDR, \
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.end = MX2x_SSI ## ssin ## _BASE_ADDR + 0x6f, \
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.flags = IORESOURCE_MEM, \
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}, { \
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.start = MX2x_INT_SSI1, \
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.end = MX2x_INT_SSI1, \
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.flags = IORESOURCE_IRQ, \
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}, \
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DEFINE_IMX_SSI_DMARES("tx0", ssin, TX0), \
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DEFINE_IMX_SSI_DMARES("rx0", ssin, RX0), \
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DEFINE_IMX_SSI_DMARES("tx1", ssin, TX1), \
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DEFINE_IMX_SSI_DMARES("rx1", ssin, RX1), \
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}; \
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\
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struct platform_device imx_ssi_device ## n = { \
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.name = "imx-ssi", \
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.id = n, \
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.num_resources = ARRAY_SIZE(imx_ssi_resources ## n), \
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.resource = imx_ssi_resources ## n, \
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}
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DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
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DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
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/* GPIO port description */
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#define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \
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{ \
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.chip.label = "gpio-" #n, \
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.irq = _irq, \
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.base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
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n * 0x100), \
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.virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
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}
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#define DEFINE_MXC_GPIO_PORT(SOC, n) \
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{ \
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.chip.label = "gpio-" #n, \
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.base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
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n * 0x100), \
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.virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
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}
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#define DEFINE_MXC_GPIO_PORTS(SOC, pfx) \
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static struct mxc_gpio_port pfx ## _gpio_ports[] = { \
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DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO), \
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DEFINE_MXC_GPIO_PORT(SOC, 1), \
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DEFINE_MXC_GPIO_PORT(SOC, 2), \
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DEFINE_MXC_GPIO_PORT(SOC, 3), \
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DEFINE_MXC_GPIO_PORT(SOC, 4), \
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DEFINE_MXC_GPIO_PORT(SOC, 5), \
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}
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#ifdef CONFIG_MACH_MX21
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DEFINE_MXC_GPIO_PORTS(MX21, imx21);
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#endif
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#ifdef CONFIG_MACH_MX27
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DEFINE_MXC_GPIO_PORTS(MX27, imx27);
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#endif
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int __init mxc_register_gpios(void)
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{
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#ifdef CONFIG_MACH_MX21
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if (cpu_is_mx21())
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return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
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else
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#endif
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#ifdef CONFIG_MACH_MX27
|
|
if (cpu_is_mx27())
|
|
return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
|
|
else
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_MACH_MX21
|
|
static struct resource mx21_usbhc_resources[] = {
|
|
{
|
|
.start = MX21_BASE_ADDR,
|
|
.end = MX21_BASE_ADDR + 0x1FFF,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
.start = MX21_INT_USBHOST,
|
|
.end = MX21_INT_USBHOST,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
struct platform_device mx21_usbhc_device = {
|
|
.name = "imx21-hcd",
|
|
.id = 0,
|
|
.dev = {
|
|
.dma_mask = &mx21_usbhc_device.dev.coherent_dma_mask,
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
},
|
|
.num_resources = ARRAY_SIZE(mx21_usbhc_resources),
|
|
.resource = mx21_usbhc_resources,
|
|
};
|
|
#endif
|
|
|