21cb20d758
Our SMP cache flush ops use CPU cross calls to deal with things like I-cache accesses not being broadcast in hardware, so ensure that the CACHE_FLUSH_IS_SAFE reflects this. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
37 lines
812 B
C
37 lines
812 B
C
#ifndef __ASM_SH_KGDB_H
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#define __ASM_SH_KGDB_H
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#include <asm/cacheflush.h>
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#include <asm/ptrace.h>
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enum regnames {
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GDB_R0, GDB_R1, GDB_R2, GDB_R3, GDB_R4, GDB_R5, GDB_R6, GDB_R7,
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GDB_R8, GDB_R9, GDB_R10, GDB_R11, GDB_R12, GDB_R13, GDB_R14, GDB_R15,
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GDB_PC, GDB_PR, GDB_SR, GDB_GBR, GDB_MACH, GDB_MACL, GDB_VBR,
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};
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#define _GP_REGS 16
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#define _EXTRA_REGS 7
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#define GDB_SIZEOF_REG sizeof(u32)
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#define DBG_MAX_REG_NUM (_GP_REGS + _EXTRA_REGS)
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#define NUMREGBYTES (DBG_MAX_REG_NUM * sizeof(GDB_SIZEOF_REG))
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static inline void arch_kgdb_breakpoint(void)
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{
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__asm__ __volatile__ ("trapa #0x3c\n");
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}
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#define BREAK_INSTR_SIZE 2
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#define BUFMAX 2048
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#ifdef CONFIG_SMP
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# define CACHE_FLUSH_IS_SAFE 0
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#else
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# define CACHE_FLUSH_IS_SAFE 1
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#endif
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#define GDB_ADJUSTS_BREAK_OFFSET
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#endif /* __ASM_SH_KGDB_H */
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