 f31dd9443a
			
		
	
	
	f31dd9443a
	
	
	
		
			
			The original MPIC MSI bank contains 8 registers, MPIC v4.3 MSI bank contains 16 registers, and this patch adds NR_MSI_REG_MAX and NR_MSI_IRQS_MAX to describe the maximum capability of MSI bank. MPIC v4.3 provides MSIIR1 to index these 16 MSI registers. MSIIR1 uses different bits definition than MSIIR. This patch adds ibs_shift and srs_shift to indicate the bits definition of the MSIIR and MSIIR1, so the same code can handle the MSIIR and MSIIR1 simultaneously. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> [scottwood@freescale.com: reinstated static on all_avail] Signed-off-by: Scott Wood <scottwood@freescale.com>
		
			
				
	
	
		
			50 lines
		
	
	
	
		
			1.4 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			50 lines
		
	
	
	
		
			1.4 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * Copyright (C) 2007-2008 Freescale Semiconductor, Inc. All rights reserved.
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|  *
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|  * Author: Tony Li <tony.li@freescale.com>
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|  *	   Jason Jin <Jason.jin@freescale.com>
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|  *
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|  * This program is free software; you can redistribute it and/or
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|  * modify it under the terms of the GNU General Public License
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|  * as published by the Free Software Foundation; version 2 of the
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|  * License.
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|  *
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|  */
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| #ifndef _POWERPC_SYSDEV_FSL_MSI_H
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| #define _POWERPC_SYSDEV_FSL_MSI_H
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| 
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| #include <linux/of.h>
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| #include <asm/msi_bitmap.h>
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| 
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| #define NR_MSI_REG_MSIIR	8  /* MSIIR can index 8 MSI registers */
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| #define NR_MSI_REG_MSIIR1	16 /* MSIIR1 can index 16 MSI registers */
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| #define NR_MSI_REG_MAX		NR_MSI_REG_MSIIR1
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| #define IRQS_PER_MSI_REG	32
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| #define NR_MSI_IRQS_MAX	(NR_MSI_REG_MAX * IRQS_PER_MSI_REG)
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| 
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| #define FSL_PIC_IP_MASK   0x0000000F
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| #define FSL_PIC_IP_MPIC   0x00000001
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| #define FSL_PIC_IP_IPIC   0x00000002
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| #define FSL_PIC_IP_VMPIC  0x00000003
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| 
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| struct fsl_msi {
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| 	struct irq_domain *irqhost;
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| 
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| 	unsigned long cascade_irq;
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| 
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| 	u32 msiir_offset; /* Offset of MSIIR, relative to start of CCSR */
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| 	u32 ibs_shift; /* Shift of interrupt bit select */
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| 	u32 srs_shift; /* Shift of the shared interrupt register select */
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| 	void __iomem *msi_regs;
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| 	u32 feature;
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| 	int msi_virqs[NR_MSI_REG_MAX];
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| 
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| 	struct msi_bitmap bitmap;
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| 
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| 	struct list_head list;          /* support multiple MSI banks */
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| 
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| 	phandle phandle;
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| };
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| 
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| #endif /* _POWERPC_SYSDEV_FSL_MSI_H */
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| 
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