41151e77a4
Enable hugepages on Freescale BookE processors. This allows the kernel to use huge TLB entries to map pages, which can greatly reduce the number of TLB misses and the amount of TLB thrashing experienced by applications with large memory footprints. Care should be taken when using this on FSL processors, as the number of large TLB entries supported by the core is low (16-64) on current processors. The supported set of hugepage sizes include 4m, 16m, 64m, 256m, and 1g. Page sizes larger than the max zone size are called "gigantic" pages and must be allocated on the command line (and cannot be deallocated). This is currently only fully implemented for Freescale 32-bit BookE processors, but there is some infrastructure in the code for 64-bit BooKE. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
87 lines
2.8 KiB
C
87 lines
2.8 KiB
C
#ifndef _ASM_POWERPC_PTE_BOOK3E_H
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#define _ASM_POWERPC_PTE_BOOK3E_H
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#ifdef __KERNEL__
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/* PTE bit definitions for processors compliant to the Book3E
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* architecture 2.06 or later. The position of the PTE bits
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* matches the HW definition of the optional Embedded Page Table
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* category.
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*/
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/* Architected bits */
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#define _PAGE_PRESENT 0x000001 /* software: pte contains a translation */
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#define _PAGE_FILE 0x000002 /* (!present only) software: pte holds file offset */
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#define _PAGE_SW1 0x000002
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#define _PAGE_BAP_SR 0x000004
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#define _PAGE_BAP_UR 0x000008
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#define _PAGE_BAP_SW 0x000010
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#define _PAGE_BAP_UW 0x000020
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#define _PAGE_BAP_SX 0x000040
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#define _PAGE_BAP_UX 0x000080
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#define _PAGE_PSIZE_MSK 0x000f00
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#define _PAGE_PSIZE_4K 0x000200
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#define _PAGE_PSIZE_8K 0x000300
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#define _PAGE_PSIZE_16K 0x000400
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#define _PAGE_PSIZE_32K 0x000500
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#define _PAGE_PSIZE_64K 0x000600
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#define _PAGE_PSIZE_128K 0x000700
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#define _PAGE_PSIZE_256K 0x000800
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#define _PAGE_PSIZE_512K 0x000900
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#define _PAGE_PSIZE_1M 0x000a00
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#define _PAGE_PSIZE_2M 0x000b00
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#define _PAGE_PSIZE_4M 0x000c00
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#define _PAGE_PSIZE_8M 0x000d00
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#define _PAGE_PSIZE_16M 0x000e00
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#define _PAGE_PSIZE_32M 0x000f00
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#define _PAGE_DIRTY 0x001000 /* C: page changed */
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#define _PAGE_SW0 0x002000
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#define _PAGE_U3 0x004000
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#define _PAGE_U2 0x008000
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#define _PAGE_U1 0x010000
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#define _PAGE_U0 0x020000
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#define _PAGE_ACCESSED 0x040000
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#define _PAGE_LENDIAN 0x080000
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#define _PAGE_GUARDED 0x100000
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#define _PAGE_COHERENT 0x200000 /* M: enforce memory coherence */
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#define _PAGE_NO_CACHE 0x400000 /* I: cache inhibit */
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#define _PAGE_WRITETHRU 0x800000 /* W: cache write-through */
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/* "Higher level" linux bit combinations */
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#define _PAGE_EXEC _PAGE_BAP_UX /* .. and was cache cleaned */
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#define _PAGE_RW (_PAGE_BAP_SW | _PAGE_BAP_UW) /* User write permission */
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#define _PAGE_KERNEL_RW (_PAGE_BAP_SW | _PAGE_BAP_SR | _PAGE_DIRTY)
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#define _PAGE_KERNEL_RO (_PAGE_BAP_SR)
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#define _PAGE_KERNEL_RWX (_PAGE_BAP_SW | _PAGE_BAP_SR | _PAGE_DIRTY | _PAGE_BAP_SX)
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#define _PAGE_KERNEL_ROX (_PAGE_BAP_SR | _PAGE_BAP_SX)
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#define _PAGE_USER (_PAGE_BAP_UR | _PAGE_BAP_SR) /* Can be read */
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#define _PAGE_HASHPTE 0
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#define _PAGE_BUSY 0
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#define _PAGE_SPECIAL _PAGE_SW0
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/* Flags to be preserved on PTE modifications */
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#define _PAGE_HPTEFLAGS _PAGE_BUSY
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/* Base page size */
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#ifdef CONFIG_PPC_64K_PAGES
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#define _PAGE_PSIZE _PAGE_PSIZE_64K
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#define PTE_RPN_SHIFT (28)
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#else
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#define _PAGE_PSIZE _PAGE_PSIZE_4K
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#define PTE_RPN_SHIFT (24)
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#endif
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#define PTE_WIMGE_SHIFT (19)
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#define PTE_BAP_SHIFT (2)
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/* On 32-bit, we never clear the top part of the PTE */
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#ifdef CONFIG_PPC32
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#define _PTE_NONE_MASK 0xffffffff00000000ULL
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#define _PMD_PRESENT 0
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#define _PMD_PRESENT_MASK (PAGE_MASK)
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#define _PMD_BAD (~PAGE_MASK)
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#endif
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_PTE_FSL_BOOKE_H */
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