 b8b572e101
			
		
	
	
	b8b572e101
	
	
	
		
			
			from include/asm-powerpc. This is the result of a mkdir arch/powerpc/include/asm git mv include/asm-powerpc/* arch/powerpc/include/asm Followed by a few documentation/comment fixups and a couple of places where <asm-powepc/...> was being used explicitly. Of the latter only one was outside the arch code and it is a driver only built for powerpc. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
		
			
				
	
	
		
			54 lines
		
	
	
	
		
			1.6 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			54 lines
		
	
	
	
		
			1.6 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
| #ifndef _ASM_POWERPC_OHARE_H
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| #define _ASM_POWERPC_OHARE_H
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| #ifdef __KERNEL__
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| /*
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|  * ohare.h: definitions for using the "O'Hare" I/O controller chip.
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|  *
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|  * Copyright (C) 1997 Paul Mackerras.
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|  *
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|  * BenH: Changed to match those of heathrow (but not all of them). Please
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|  *       check if I didn't break anything (especially the media bay).
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|  */
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| 
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| /* offset from ohare base for feature control register */
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| #define OHARE_MBCR	0x34
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| #define OHARE_FCR	0x38
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| 
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| /*
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|  * Bits in feature control register.
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|  * These were mostly derived by experiment on a powerbook 3400
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|  * and may differ for other machines.
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|  */
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| #define OH_SCC_RESET		1
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| #define OH_BAY_POWER_N		2	/* a guess */
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| #define OH_BAY_PCI_ENABLE	4	/* a guess */
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| #define OH_BAY_IDE_ENABLE	8
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| #define OH_BAY_FLOPPY_ENABLE	0x10
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| #define OH_IDE0_ENABLE		0x20
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| #define OH_IDE0_RESET_N		0x40	/* a guess */
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| #define OH_BAY_DEV_MASK		0x1c
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| #define OH_BAY_RESET_N		0x80
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| #define OH_IOBUS_ENABLE		0x100	/* IOBUS seems to be IDE */
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| #define OH_SCC_ENABLE		0x200
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| #define OH_MESH_ENABLE		0x400
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| #define OH_FLOPPY_ENABLE	0x800
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| #define OH_SCCA_IO		0x4000
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| #define OH_SCCB_IO		0x8000
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| #define OH_VIA_ENABLE		0x10000	/* Is apparently wrong, to be verified */
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| #define OH_IDE1_RESET_N		0x800000
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| 
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| /*
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|  * Bits to set in the feature control register on PowerBooks.
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|  */
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| #define PBOOK_FEATURES		(OH_IDE_ENABLE | OH_SCC_ENABLE | \
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| 				 OH_MESH_ENABLE | OH_SCCA_IO | OH_SCCB_IO)
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| 
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| /*
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|  * A magic value to put into the feature control register of the
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|  * "ohare" I/O controller on Starmaxes to enable the IDE CD interface.
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|  * Contributed by Harry Eaton.
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|  */
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| #define STARMAX_FEATURES	0xbeff7a
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| 
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| #endif /* __KERNEL__ */
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| #endif /* _ASM_POWERPC_OHARE_H */
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