e51f8f32d6
Add interrupt handling support for 64-bit bookehv hosts. Unify 32 and 64 bit implementations using a common stack layout and a common execution flow starting from kvm_handler_common macro. Update documentation for 64-bit input register values. This patch only address the bolted TLB miss exception handlers version. Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
74 lines
2.2 KiB
C
74 lines
2.2 KiB
C
/*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*/
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#ifndef ASM_KVM_BOOKE_HV_ASM_H
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#define ASM_KVM_BOOKE_HV_ASM_H
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#ifdef __ASSEMBLY__
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/*
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* All exceptions from guest state must go through KVM
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* (except for those which are delivered directly to the guest) --
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* there are no exceptions for which we fall through directly to
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* the normal host handler.
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*
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* 32-bit host
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* Expected inputs (normal exceptions):
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* SCRATCH0 = saved r10
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* r10 = thread struct
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* r11 = appropriate SRR1 variant (currently used as scratch)
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* r13 = saved CR
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* *(r10 + THREAD_NORMSAVE(0)) = saved r11
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* *(r10 + THREAD_NORMSAVE(2)) = saved r13
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*
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* Expected inputs (crit/mcheck/debug exceptions):
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* appropriate SCRATCH = saved r8
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* r8 = exception level stack frame
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* r9 = *(r8 + _CCR) = saved CR
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* r11 = appropriate SRR1 variant (currently used as scratch)
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* *(r8 + GPR9) = saved r9
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* *(r8 + GPR10) = saved r10 (r10 not yet clobbered)
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* *(r8 + GPR11) = saved r11
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*
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* 64-bit host
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* Expected inputs (GEN/GDBELL/DBG/MC exception types):
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* r10 = saved CR
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* r13 = PACA_POINTER
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* *(r13 + PACA_EX##type + EX_R10) = saved r10
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* *(r13 + PACA_EX##type + EX_R11) = saved r11
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* SPRN_SPRG_##type##_SCRATCH = saved r13
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*
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* Expected inputs (CRIT exception type):
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* r10 = saved CR
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* r13 = PACA_POINTER
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* *(r13 + PACA_EX##type + EX_R10) = saved r10
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* *(r13 + PACA_EX##type + EX_R11) = saved r11
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* *(r13 + PACA_EX##type + EX_R13) = saved r13
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*
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* Expected inputs (TLB exception type):
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* r10 = saved CR
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* r13 = PACA_POINTER
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* *(r13 + PACA_EX##type + EX_TLB_R10) = saved r10
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* *(r13 + PACA_EX##type + EX_TLB_R11) = saved r11
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* SPRN_SPRG_GEN_SCRATCH = saved r13
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*
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* Only the bolted version of TLB miss exception handlers is supported now.
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*/
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.macro DO_KVM intno srr1
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#ifdef CONFIG_KVM_BOOKE_HV
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BEGIN_FTR_SECTION
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mtocrf 0x80, r11 /* check MSR[GS] without clobbering reg */
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bf 3, 1975f
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b kvmppc_handler_\intno\()_\srr1
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1975:
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END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
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#endif
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.endm
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#endif /*__ASSEMBLY__ */
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#endif /* ASM_KVM_BOOKE_HV_ASM_H */
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